Realization of a Class of Switching Functions by Threshold-Logic Networks. - Stephen Sik-Sang Yau; Daniel L. Ostapko (IEEE Trans. Computers, 1968)

Optimum test patterns for parity networks. - Douglas C. Bossen; Daniel L. Ostapko; Arvind M. Patel (AFIPS Fall Joint Computing Conference, 1970)

Realization of an Arbitrary Switching Function with a Two-Level Network of Threshold and Parity Elements. - Daniel L. Ostapko; Stephen S. Yau (IEEE Trans. Computers, 1970)

Minimum test patterns for residue networks. - Douglas C. Bossen; Daniel L. Ostapko; Arvind M. Patel; Martin S. Schmookler (DAC, 1971)

On Complementation of Boolean Functions. - Se June Hong; Daniel L. Ostapko (IEEE Trans. Computers, 1972)

Analysis of algorithms implemented in software and hardware. - Daniel L. Ostapko (ACM Annual Conference (2), 1974)

MINI: A Heuristic Approach for Logic Minimization. - Se June Hong; Robert G. Cain; Daniel L. Ostapko (IBM J. Res. Dev., 1974)

Generating Test Examples for Heuristic Boolean Minimization. - Daniel L. Ostapko; Se June Hong (IBM J. Res. Dev., 1974)

On deriving a relation between circuits and input/output by analyzing an equivalent program. - Daniel L. Ostapko (ACM SIGPLAN Notices, 1974)

Codes for Self-Clocking, AC-Coupled Transmission: Aspects of Synthesis and Analysis. - Se June Hong; Daniel L. Ostapko (IBM J. Res. Dev., 1975)

Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's). - Daniel L. Ostapko; Se June Hong (IEEE Trans. Computers, 1979)

A Simple Procedure to Generate Optimum Test Patterns for Parity Logic Networks. - Se June Hong; Daniel L. Ostapko (IEEE Trans. Computers, 1981)

Interactive design language: A unified approach to hardware simulation, synthesis and documentation. - Leon I. Maissel; Daniel L. Ostapko (DAC, 1982)

A Mapping and Memory Chip Hardware which Provides Symmetric Reading/Writing of Horizontal and Vertical Lines. - Daniel L. Ostapko (IBM J. Res. Dev., 1984)

On the Signal Bounding Problem in Timing Analysis. - Jin-Fuw Lee; Daniel L. Ostapko; Jeffery Soreff; C. K. Wong (ICCAD, 2001)

Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis. - Howard Chen 001; Daniel L. Ostapko (PATMOS, 2004)

A Mask Reuse Methodology for Reducing System-on-a-Chip Cost. - Subhrajit Bhattacharya; John A. Darringer; Daniel L. Ostapko; Youngsoo Shin (ISQED, 2005)