SOI Implementation of a 64-Bit Adder. - J. V. Tran; Farnaz Mounes-Toussi; S. N. Storino; D. L. Stasiak (ICCD, 1999)

Custom circuit design as a driver of microprocessor performance. - David H. Allen; Sang H. Dhong; H. Peter Hofstee; Jens Leenstra; Kevin J. Nowka; Daniel L. Stasiak; Dieter F. Wendel (IBM J. Res. Dev., 2000)

A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology. - Daniel L. Stasiak; Farnaz Mounes-Toussi; Salvatore N. Storino (IEEE J. Solid State Circuits, 2001)

Cell Processor Low-Power Design Methodology. - Daniel L. Stasiak; Rajat Chaudhry; Dennis Cox; Stephen D. Posluszny; James D. Warnock; Steve Weitzel; Dieter F. Wendel; Michael Wang 001 (IEEE Micro, 2005)

A cycle accurate power estimation tool. - Rajat Chaudhry; Daniel L. Stasiak; Stephen D. Posluszny; Sang H. Dhong (ASP-DAC, 2006)

Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. - Dac C. Pham; Tony Aipperspach; David Boerstler; Mark Bolliger; Rajat Chaudhry; Dennis Cox; Paul E. Harvey; H. Peter Hofstee; Charles R. Johns; Jim Kahle; Atsushi Kameyama; John M. Keaty; et al. (IEEE J. Solid State Circuits, 2006)