Shared last-level TLBs for chip multiprocessors. - Abhishek Bhattacharjee; Daniel Lustig; Margaret Martonosi (HPCA, 2011)

Reducing GPU offload latency via fine-grained CPU-GPU synchronization. - Daniel Lustig; Margaret Martonosi (HPCA, 2013)

Triggered instructions: a control paradigm for spatially-programmed architectures. - Angshuman Parashar; Michael Pellauer; Michael Adler; Bushra Ahsan; Neal Clayton Crago; Daniel Lustig; Vladimir Pavlov; Antonia Zhai; Mohit Gambhir; Aamer Jaleel; Randy L. Allmon; Rachid Rayess; et al. (ISCA, 2013)

TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs. - Daniel Lustig; Abhishek Bhattacharjee; Margaret Martonosi (ACM Trans. Archit. Code Optim., 2013)

Pipe Check: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models. - Daniel Lustig; Michael Pellauer; Margaret Martonosi (MICRO, 2014)

Efficient Spatial Processing Element Control via Triggered Instructions. - Angshuman Parashar; Michael Pellauer; Michael Adler; Bushra Ahsan; Neal Clayton Crago; Daniel Lustig; Vladimir Pavlov; Antonia Zhai; Mohit Gambhir; Aamer Jaleel; Randy L. Allmon; Rachid Rayess; et al. (IEEE Micro, 2014)

ArMOR: defending against memory consistency model mismatches in heterogeneous architectures. - Daniel Lustig; Caroline Trippel; Michael Pellauer; Margaret Martonosi (ISCA, 2015)

CCICheck: using µhb graphs to verify the coherence-consistency interface. - Yatin A. Manerkar; Daniel Lustig; Michael Pellauer; Margaret Martonosi (MICRO, 2015)

Verifying Correct Microarchitectural Enforcement of Memory Consistency Models. - Daniel Lustig; Michael Pellauer; Margaret Martonosi (IEEE Micro, 2015)

Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures. - Michael Pellauer; Angshuman Parashar; Michael Adler; Bushra Ahsan; Randy L. Allmon; Neal Clayton Crago; Kermin Fleming; Mohit Gambhir; Aamer Jaleel; Tushar Krishna; Daniel Lustig; Stephen Maresh; et al. (ACM Trans. Comput. Syst., 2015)

Specifying, Verifying, and Translating Between Memory Consistency Models - Daniel Lustig (2015)

COATCheck: Verifying Memory Ordering at the Hardware-OS Interface. - Daniel Lustig; Geet Sethi; Margaret Martonosi; Abhishek Bhattacharjee (ASPLOS, 2016)

Counterexamples and Proof Loophole for the C/C++ to POWER and ARMv7 Trailing-Sync Compiler Mappings. - Yatin A. Manerkar; Caroline Trippel; Daniel Lustig; Michael Pellauer; Margaret Martonosi (CoRR, 2016)

Exploring the Trisection of Software, Hardware, and ISA in Memory Model Design. - Caroline Trippel; Yatin A. Manerkar; Daniel Lustig; Michael Pellauer; Margaret Martonosi (CoRR, 2016)

Automated Synthesis of Comprehensive Memory Model Litmus Test Suites. - Daniel Lustig; Andrew Wright; Alexandros Papakonstantinou; Olivier Giroux (ASPLOS, 2017)

TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA. - Caroline Trippel; Yatin A. Manerkar; Daniel Lustig; Michael Pellauer; Margaret Martonosi (ASPLOS, 2017)

RTLcheck: verifying the memory consistency of RTL designs. - Yatin A. Manerkar; Daniel Lustig; Margaret Martonosi; Michael Pellauer (MICRO, 2017)

Weak Memory Models with Matching Axiomatic and Operational Definitions. - Sizhuo Zhang; Muralidaran Vijayaraghavan; Dan Lustig; Arvind 001 (CoRR, 2017)

Transistency Models: Memory Ordering at the Hardware-OS Interface. - Daniel Lustig; Geet Sethi; Abhishek Bhattacharjee; Margaret Martonosi (IEEE Micro, 2017)

Architectural and Operating System Support for Virtual Memory - Abhishek Bhattacharjee; Daniel Lustig (Morgan & Claypool Publishers, 2017)

PipeProof: Automated Memory Consistency Proofs for Microarchitectural Specifications. - Yatin A. Manerkar; Daniel Lustig; Margaret Martonosi; Aarti Gupta (MICRO, 2018)

CheckMate: Automated Synthesis of Hardware Exploits and Security Litmus Tests. - Caroline Trippel; Daniel Lustig; Margaret Martonosi (MICRO, 2018)

MeltdownPrime and SpectrePrime: Automatically-Synthesized Attacks Exploiting Invalidation-Based Coherence Protocols. - Caroline Trippel; Daniel Lustig; Margaret Martonosi (CoRR, 2018)

Full-Stack Memory Model Verification with TriCheck. - Caroline Trippel; Yatin A. Manerkar; Daniel Lustig; Michael Pellauer; Margaret Martonosi (IEEE Micro, 2018)

A Formal Analysis of the NVIDIA PTX Memory Consistency Model. - Daniel Lustig; Sameer Sahasrabuddhe; Olivier Giroux (ASPLOS, 2019)

Nimble Page Management for Tiered Memory Systems. - Zi Yan; Daniel Lustig; David W. Nellans; Abhishek Bhattacharjee (ASPLOS, 2019)

Translation ranger: operating system support for contiguity-aware TLBs. - Zi Yan; Daniel Lustig; David W. Nellans; Abhishek Bhattacharjee (ISCA, 2019)

Security Verification via Automatic Hardware-Aware Exploit Synthesis: The CheckMate Approach. - Caroline Trippel; Daniel Lustig; Margaret Martonosi (IEEE Micro, 2019)

HMG: Extending Cache Coherence Protocols Across Modern Hierarchical Multi-GPU Systems. - Xiaowei Ren; Daniel Lustig; Evgeny Bolotin; Aamer Jaleel; Oreste Villa; David W. Nellans (HPCA, 2020)

RealityCheck: Bringing Modularity, Hierarchy, and Abstraction to Automated Microarchitectural Memory Consistency Verification. - Yatin A. Manerkar; Daniel Lustig; Margaret Martonosi (CoRR, 2020)

Need for Speed: Experiences Building a Trustworthy System-Level GPU Simulator. - Oreste Villa; Daniel Lustig; Zi Yan; Evgeny Bolotin; Yaosheng Fu; Niladrish Chatterjee; Nan Jiang 009; David W. Nellans (HPCA, 2021)

Efficient Multi-GPU Shared Memory via Automatic Optimization of Fine-Grained Transfers. - Harini Muthukrishnan; David W. Nellans; Daniel Lustig; Jeffrey A. Fessler; Thomas F. Wenisch (ISCA, 2021)

GPS: A Global Publish-Subscribe Model for Multi-GPU Memory Management. - Harini Muthukrishnan; Daniel Lustig; David W. Nellans; Thomas F. Wenisch (MICRO, 2021)

Mixed-proxy extensions for the NVIDIA PTX memory consistency model: industrial product. - Daniel Lustig; Simon Cooksey; Olivier Giroux (ISCA, 2022)

Parsimony: Enabling SIMD/Vector Programming in Standard Compiler Flows. - Vijay Kandiah; Daniel Lustig; Oreste Villa; David W. Nellans; Nikos Hardavellas (CGO, 2023)

FinePack: Transparently Improving the Efficiency of Fine-Grained Transfers in Multi-GPU Systems. - Harini Muthukrishnan; Daniel Lustig; Oreste Villa; Thomas F. Wenisch; David W. Nellans (HPCA, 2023)