High-speed interconnect and packaging design of the IBM System z9 processor cage. - Hubert Harrer; Daniel M. Dreps; Thomas-Michael Winkel; Wolfgang Scholz; Bao G. Truong; Andreas Huber; Tingdong Zhou; Kenneth L. Christian; Gary F. Goth (IBM J. Res. Dev., 2007)

Low power passive equalizer optimization using tritonic step response. - Ling Zhang; Wenjian Yu; Haikun Zhu; Alina Deutsch; George A. Katopis; Daniel M. Dreps; Ernest S. Kuh; Chung-Kuan Cheng (DAC, 2008)

Low Power Passive Equalizer Design for Computer Memory Links. - Ling Zhang; Wenjian Yu; Yulei Zhang 002; Renshen Wang; Alina Deutsch; George A. Katopis; Daniel M. Dreps; James F. Buckwalter; Ernest S. Kuh; Chung-Kuan Cheng (Hot Interconnects, 2008)

A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator. - Kyu-Hyoun Kim; Paul W. Coteus; Daniel M. Dreps; Seongwon Kim; Sergey V. Rylov; Daniel J. Friedman (ISSCC, 2008)

Design methodology of high performance on-chip global interconnect using terminated transmission-line. - Yulei Zhang 002; Ling Zhang; Alina Deutsch; George A. Katopis; Daniel M. Dreps; James F. Buckwalter; Ernest S. Kuh; Chung-Kuan Cheng (ISQED, 2009)

A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS. - Kyu-Hyoun Kim; Daniel M. Dreps; Frank D. Ferraiolo; Paul W. Coteus; Seongwon Kim; Sergey V. Rylov; Daniel J. Friedman (ISSCC, 2009)

Packaging design challenges of the IBM System z10 Enterprise Class server. - Thomas-Michael Winkel; Hubert Harrer; Dierk Kaller; Jochen Supper; Daniel M. Dreps; Kenneth L. Christian; D. Cosmadelis; Tingdong Zhou; Thomas Strach; J. Ludwig; David L. Edwards (IBM J. Res. Dev., 2009)

The IBM POWER7 HUB module: A terabyte interconnect switch for high-performance computer systems. - L. Baba Arimilli; Steve Baumgartner; Scott Clark; Daniel Dreps; David W. Siljenberg; Andrew Maki (Hot Chips Symposium, 2010)

A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS. - Robert Reutemann; Michael Ruegg; Fran Keyser; John Bergkvist; Daniel Dreps; Thomas Toifl; Martin L. Schmatz (ISSCC, 2010)

Channel Optimization for the Design of High Speed I/O links. - Rohan Mandrekar; Yaping Zhou; Sungjun Chun; Anand Haridass; Jinwoo Choi; Nanju Na; Daniel M. Dreps; Roger D. Weekly; Paul Harvey (VLSI Design, 2010)

A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS. - Robert Reutemann; Michael Ruegg; Fran Keyser; John Bergkvist; Daniel Dreps; Thomas Toifl; Martin L. Schmatz (IEEE J. Solid State Circuits, 2010)

POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. - Dieter F. Wendel; Ronald N. Kalla; James D. Warnock; Robert Cargnoni; Sam G. Chu; Joachim G. Clabes; Daniel Dreps; David Hrusecky; Joshua Friedrich; Md. Saiful Islam 004; James A. Kahle; Jens Leenstra; et al. (IEEE J. Solid State Circuits, 2011)

A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS. - Thomas Toifl; Christian Menolfi; Michael Ruegg; Robert Reutemann; Daniel Dreps; Troy J. Beukema; Andrea Prati 002; Daniele Gardellini; Marcel A. Kossel; Peter Buchmann; Matthias Braendli; Pier Andrea Francese; et al. (IEEE J. Solid State Circuits, 2012)

The POWER8TM processor: Designed for big data, analytics, and cloud environments. - Joshua Friedrich; Hung Q. Le; William J. Starke; Jeff Stuecheli; Balaram Sinharoy; Eric J. Fluhr; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; David Hogenmiller; Frank Malgioglio; et al. (ICICDT, 2014)

5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. - Eric J. Fluhr; Joshua Friedrich; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; Allen Hall; David Hogenmiller; Frank Malgioglio; Ryan Nett; Jose Paredes; Juergen Pille; et al. (ISSCC, 2014)

4.1 22nm Next-generation IBM System z microprocessor. - James D. Warnock; Brian W. Curran; John Badar; Gregory Fredeman; Donald W. Plass; Yuen H. Chan; Sean M. Carey; Gerard Salem; Friedrich Schroeder; Frank Malgioglio; Guenter Mayer; Christopher J. Berry; et al. (ISSCC, 2015)

How server designs will change as interface bandwidth demands continue to increase. - Daniel Dreps (OFC, 2015)

IBM POWER8 circuit design and energy optimization. - Victor V. Zyuban; Joshua Friedrich; Daniel M. Dreps; Jürgen Pille; Donald W. Plass; Phillip J. Restle; Zeynep Toprak Deniz; Matthew M. Ziegler; Sam G. Chu; Md. Saiful Islam 004; James D. Warnock; Bob Philhower; et al. (IBM J. Res. Dev., 2015)

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. - Eric J. Fluhr; Steve Baumgartner; David W. Boerstler; John F. Bulzacchelli; Timothy Diemoz; Daniel Dreps; George English; Joshua Friedrich; Anne Gattiker; Tilman Gloekler; Christopher J. Gonzalez; Jason Hibbeler; et al. (IEEE J. Solid State Circuits, 2015)

3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4. - Christopher J. Gonzalez; Eric Fluhr; Daniel Dreps; David Hogenmiller; Rahul M. Rao; Jose Paredes; Michael S. Floyd; Michael A. Sperling; Ryan Kruse; Vinod Ramadurai; Ryan Nett; Md. Saiful Islam 004; et al. (ISSCC, 2017)

Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor. - Bharat Sukhwani; Thomas Roewer; Charles L. Haymes; Kyu-Hyoun Kim; Adam J. McPadden; Daniel M. Dreps; Dean Sanner; Jan van Lunteren; Sameh W. Asaad (MICRO, 2017)

IBM POWER9 package technology and design. - Sungjun Chun; Wiren Dale Becker; Jon Casey; Steve Ostrander; Daniel Dreps; Jose Ale Hejase; Ryan Nett; Brian Beaman; Jason R. Eagle (IBM J. Res. Dev., 2018)

IBM POWER9 opens up a new era of acceleration enablement: OpenCAPI. - Jeffrey Stuecheli; William J. Starke; John D. Irish; L. Baba Arimilli; Daniel M. Dreps; Bart Blaner; Curt Wollbrink; Brian Allison (IBM J. Res. Dev., 2018)

The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. - Christopher J. Gonzalez; Michael S. Floyd; Eric Fluhr; Phillip J. Restle; Daniel Dreps; Michael A. Sperling; Rahul M. Rao; David Hogenmiller; Christos Vezyrtzis; Pierce Chuang; Daniel Lewis; Ricardo Escobar; et al. (IEEE J. Solid State Circuits, 2018)

Summit and Sierra: Designing AI/HPC Supercomputers. - James A. Kahle; Jaime Moreno 002; Daniel Dreps (ISSCC, 2019)

A 25×50Gb/s 2.22pJ/b NRZ RX with Dual-Bank and 3-Tap Speculative DFE for Microprocessor Application in 7nm FinFET CMOS. - Yang You; Glen A. Wiedemeier; Chad Marquart; Chris Steffen; Erik English; Dereje Yilma; Thomas Pham; Venkat Nammi; Jeffrey Okyere; Nathan Blanchard; Akil Sutton; Ze Zhang; et al. (VLSI Circuits, 2020)

POWER10™: A 16-Core SMT8 Server Processor With 2TB/s Off-Chip Bandwidth in 7nm Technology. - Rahul M. Rao; Christopher J. Gonzalez; Eric Fluhr; Abraham Mathews; Andrew Bianchi; Daniel Dreps; David Wolpert 001; Eric Lai; Gerald Strevig; Glen A. Wiedemeier; Philipp Salz; Ryan Kruse (ISSCC, 2022)