The Organization of the Cedar System. - Jeff Konicek; Tracy Tilton; Alexander V. Veidenbaum; Chuan-Qi Zhu; Edward S. Davidson; Ruppert A. Downing; Michael J. Haney; Manish Sharma; Pen-Chung Yew; P. Michael Farmwald; David J. Kuck; Daniel M. Lavery; et al. (ICPP (1), 1991)

Using Profile Information to Assist Advaced Compiler Optimization and Scheduling. - William Y. Chen; Roger A. Bringmann; Scott A. Mahlke; Sadun Anik; Tokuzo Kiyohara; Nancy J. Warter; Daniel M. Lavery; Wen-mei W. Hwu; Richard E. Hank; John C. Gyllenhaal (LCPC, 1992)

The superblock: An effective technique for VLIW and superscalar compilation. - Wen-mei W. Hwu; Scott A. Mahlke; William Y. Chen; Pohua P. Chang; Nancy J. Warter; Roger A. Bringmann; Roland G. Ouellette; Richard E. Hank; Tokuzo Kiyohara; Grant E. Haab; John G. Holm; Daniel M. Lavery (J. Supercomput., 1993)

Unrolling-based optimizations for modulo scheduling. - Daniel M. Lavery; Wen-mei W. Hwu (MICRO, 1995)

Compiler technology for future microprocessors. - Wen-Mei W. Hwu; Richard E. Hank; David M. Gallagher; Scott A. Mahlke; Daniel M. Lavery; Grant E. Haab; John C. Gyllenhaal; David I. August (Proc. IEEE, 1995)

The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors. - Pohua P. Chang; Daniel M. Lavery; Scott A. Mahlke; William Y. Chen; Wen-mei W. Hwu (IEEE Trans. Computers, 1995)

Modulo Scheduling of Loops in Control-intensive Non-numeric Programs. - Daniel M. Lavery; Wen-mei W. Hwu (MICRO, 1996)

Modulo Scheduling for Control-Intensive General-Purpose Programs - Daniel M. Lavery (1997)

An Advanced Optimizer for the IA-64 Architecture. - Rakesh Krishnaiyer; Dattatraya Kulkarni; Daniel M. Lavery; Wei Li 015; Chu-Cheow Lim; John Ng; David C. Sehr (IEEE Micro, 2000)

Speculative precomputation: long-range prefetching of delinquent loads. - Jamison D. Collins; Hong Wang 003; Dean M. Tullsen; Christopher J. Hughes; Yong-Fong Lee; Daniel M. Lavery; John Paul Shen (ISCA, 2001)

On the Importance of Points-to Analysis and Other Memory Disambiguation Methods for C Programs. - Rakesh Ghiya; Daniel M. Lavery; David C. Sehr (PLDI, 2001)

Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors. - R. David Weldon; Steven S. Chang; Hong Wang 003; Gerolf Hoflehner; Perry H. Wang; Daniel M. Lavery; John Paul Shen (Interaction between Compilers and Computer Architectures, 2002)

Post-Pass Binary Adaptation for Software-Based Speculative Precomputation. - Shih-Wei Liao; Perry H. Wang; Hong Wang 003; John Paul Shen; Gerolf Hoflehner; Daniel M. Lavery (PLDI, 2002)

Optimizations to Prevent Cache Penalties for the Intel ® Itanium 2 Processor. - Jean-Francois Collard; Daniel M. Lavery (CGO, 2003)

Optimization for the Intel® Itanium ®Architectur Register Stack. - Alex Settle; Daniel A. Connors; Gerolf Hoflehner; Daniel M. Lavery (CGO, 2003)

The compiler as a validation and evaluation tool. - Gerolf Hoflehner; Daniel M. Lavery; David C. Sehr (COCV@ETAPS, 2003)

Compiler Optimizations for Transaction Processing Workloads on Itanium® Linux Systems. - Gerolf Hoflehner; Knud Kirkegaard; Rod Skinner; Daniel M. Lavery; Yong-Fong Lee; Wei Li 015 (MICRO, 2004)

Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture. - Arun Kejariwal; Gerolf Hoflehner; Darshan Desai; Daniel M. Lavery; Alexandru Nicolau; Alexander V. Veidenbaum (SIGMETRICS, 2007)

Performance Characterization of Itanium® 2-Based Montecito Processor. - Darshan Desai; Gerolf Hoflehner; Arun Kejariwal; Daniel M. Lavery; Alexandru Nicolau; Alexander V. Veidenbaum; Cameron McNairy (SPEC Benchmark Workshop, 2009)

Programming Spiking Neural Networks on Intel's Loihi. - Chit-Kwan Lin; Andreas Wild; Gautham N. Chinya; Yongqiang Cao; Mike Davies 002; Daniel M. Lavery; Hong Wang (Computer, 2018)