Signal processing strategies with the TDEMI measurement system. - Florian Krug; Daniel Mueller 001; Peter Russer (IEEE Trans. Instrum. Meas., 2004)

Deterministic approaches to analog performance space exploration (PSE). - Daniel Mueller 001; Guido Stehr; Helmut E. Graeb; Ulf Schlichtmann (DAC, 2005)

Eigenschaftsraumexploration bei der hierarchischen Dimensionierung analoger integrierter Schaltungen. - Daniel Mueller 001; Guido Stehr; Helmut E. Graeb; Ulf Schlichtmann (GI Jahrestagung (1), 2005)

A CPPLL hierarchical optimization methodology considering jitter, power and locking time. - Jun Zou; Daniel Mueller 001; Helmut E. Graeb; Ulf Schlichtmann (DAC, 2006)

Fast evaluation of analog circuit structures by polytopal approximations. - Daniel Mueller 001; Guido Stehr; Helmut E. Graeb; Ulf Schlichtmann (ISCAS, 2006)

Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts. - Jun Zou; Helmut Graeb; Daniel Mueller 001; Ulf Schlichtmann (CICC, 2007)

Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming. - Daniel Mueller 001; Helmut E. Graeb; Ulf Schlichtmann (DATE, 2007)

Pareto-Front Computation and Automatic Sizing of CPPLLs. - Jun Zou; Daniel Mueller 001; Helmut E. Graeb; Ulf Schlichtmann (ISQED, 2007)

Pareto optimization of analog circuits considering variability. - Helmut Graeb; Daniel Mueller-Gritschneder; Ulf Schlichtmann (Int. J. Circuit Theory Appl., 2009)

A Successive Approach to Compute the Bounded Pareto Front of Practical Multiobjective Optimization Problems. - Daniel Mueller-Gritschneder; Helmut E. Graeb; Ulf Schlichtmann (SIAM J. Optim., 2009)

Computation of yield-optimized Pareto fronts for analog integrated circuit specifications. - Daniel Mueller-Gritschneder; Helmut Graeb (DATE, 2010)

Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction Level. - Daniel Mueller-Gritschneder; Kun Lu 005; Ulf Schlichtmann (DSD, 2011)

Removal of unnecessary context switches from the systemc simulation kernel for fast VP simulation. - Kun Lu 005; Daniel Mueller-Gritschneder; Ulf Schlichtmann (ICSAMOS, 2011)

Accurately timed transaction level models for virtual prototyping at high abstraction level. - Kun Lu 005; Daniel Mueller-Gritschneder; Ulf Schlichtmann (DATE, 2012)

Automated construction of a cycle-approximate transaction level model of a memory controller. - Vladimir Todorov; Daniel Mueller-Gritschneder; Helmut Reinig; Ulf Schlichtmann (DATE, 2012)

Hierarchical control flow matching for source-level simulation of embedded software. - Kun Lu 005; Daniel Müller-Gritschneder; Ulf Schlichtmann (ISSoC, 2012)

Memory access reconstruction based on memory allocation mechanism for source-level simulation of embedded software. - Kun Lu 005; Daniel Mueller-Gritschneder; Ulf Schlichtmann (ASP-DAC, 2013)

Fast cache simulation for host-compiled simulation of embedded software. - Kun Lu 005; Daniel Mueller-Gritschneder; Ulf Schlichtmann (DATE, 2013)

Analytical timing estimation for temporally decoupled TLMs considering resource conflicts. - Kun Lu 005; Daniel Mueller-Gritschneder; Ulf Schlichtmann (DATE, 2013)

A virtual prototyping platform for real-time systems with a case study for a two-wheeled robot. - Daniel Mueller-Gritschneder; Kun Lu 005; Erik Wallander; Marc Greim; Ulf Schlichtmann (DATE, 2013)

A spectral clustering approach to application-specific network-on-chip synthesis. - Vladimir Todorov; Daniel Mueller-Gritschneder; Helmut Reinig; Ulf Schlichtmann (DATE, 2013)

Technology-aware system failure analysis in the presence of soft errors by Mixture Importance Sampling. - Veit Kleeberger; Daniel Mueller-Gritschneder; Ulf Schlichtmann (DFTS, 2013)

A greedy approach for latency-bounded deadlock-free routing path allocation for application-specific NoCs. - Amit Verma; Pritpal S. Multani; Daniel Mueller-Gritschneder; Vladimir Todorov; Ulf Schlichtmann (NOCS, 2013)

Application of Dempster-Shafer Theory to task mapping under epistemic uncertainty. - Carsten Uphoff; Daniel Mueller-Gritschneder; Ulf Schlichtmann (SysCon, 2013)

A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience. - Veit Kleeberger; Christina Gimmler-Dumont; Christian Weis; Andreas Herkersdorf; Daniel Mueller-Gritschneder; Sani R. Nassif; Ulf Schlichtmann; Norbert Wehn (IEEE Micro, 2013)

Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges. - Jan-Hendrik Oetjens; Nico Bannow; Markus Becker 001; Oliver Bringmann 001; Andreas Burger; Moomen Chaari; Samarjit Chakraborty; Rolf Drechsler; Wolfgang Ecker; Kim Grüttner; Thomas Kruse; Christoph Kuznik; et al. (DAC, 2014)

Fault-tolerant embedded control systems for unreliable hardware. - Dip Goswami; Daniel Mueller-Gritschneder; Twan Basten; Ulf Schlichtmann; Samarjit Chakraborty (ISIC, 2014)

System C-based multi-level error injection for the evaluation of fault-tolerant systems. - Daniel Mueller-Gritschneder; Petra R. Maier; Marc Greim; Ulf Schlichtmann (ISIC, 2014)

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience. - Andreas Herkersdorf; Hananeh Aliee; Michael Engel; Michael Glaß; Christina Gimmler-Dumont; Jörg Henkel; Veit Kleeberger; Michael A. Kochte; Johannes Maximilian Kühn; Daniel Mueller-Gritschneder; Sani R. Nassif; Holm Rauchfuss; et al. (Microelectron. Reliab., 2014)

Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies. - Vladimir Todorov; Daniel Mueller-Gritschneder; Helmut Reinig; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

GRIP: grammar-based IP integration and packaging for acceleration-rich SoC designs. - Munish Jassi; Daniel Müller-Gritschneder; Ulf Schlichtmann (DAC, 2015)

The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems. - Oliver Bringmann 001; Wolfgang Ecker; Andreas Gerstlauer; Ajay Goyal; Daniel Mueller-Gritschneder; Prasanth Sasidharan; Simranjit Singh (DATE, 2015)

Automatic ILP-based Firewall Insertion for Secure Application-Specific Networks-on-Chip. - Yong Hu; Daniel Müller-Gritschneder; Martha Johanna Sepúlveda; Guy Gogniat; Ulf Schlichtmann (INA-OCMC@HiPEAC, 2015)

Application-aware cross-layer reliability analysis and optimization. - Michael Glaß; Hananeh Aliee; Liang Chen 014; Mojtaba Ebrahimi; Faramarz Khosravi; Veit B. Kleeberger; Alexandra Listl; Daniel Müller-Gritschneder; Fabian Oboril; Ulf Schlichtmann; Mehdi Baradaran Tahoori; Jürgen Teich; et al. (it Inf. Technol., 2015)

Fault injection at host-compiled level with static fault set reduction for SoC firmware robustness testing. - Petra R. Maier; Veit Kleeberger; Daniel Mueller-Gritschneder; Ulf Schlichtmann (CODES+ISSS, 2016)

Hardware-Accelerated Software Library Drivers Generation for IP-Centric SoC Designs. - Munish Jassi; Uzair Sharif; Daniel Müller-Gritschneder; Ulf Schlichtmann (ACM Great Lakes Symposium on VLSI, 2016)

Safety evaluation based on virtual prototypes: Fault injection with multi-level processor models. - Daniel Mueller-Gritschneder; Marc Greim; Ulf Schlichtmann (ISIC, 2016)

Model-based framework for networks-on-chip design space exploration. - Yong Hu; Daniel Müller-Gritschneder; Ulf Schlichtmann (AISTECS@HiPEAC, 2017)

The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. - Daniel Mueller-Gritschneder; Keerthikumara Devarajegowda; Martin Dittrich; Wolfgang Ecker; Marc Greim; Ulf Schlichtmann (RSP, 2017)

Host-Compiled Simulation. - Daniel Mueller-Gritschneder; Andreas Gerstlauer (Handbook of Hardware/Software Codesign, 2017)

Design and validation of fault-tolerant embedded controllers. - Saurav Kumar Ghosh; Soumyajit Dey; Dip Goswami; Daniel Mueller-Gritschneder; Samarjit Chakraborty (DATE, 2018)

ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques. - Daniel Mueller-Gritschneder; Martin Dittrich; Josef Weinzierl; Eric Cheng; Subhasish Mitra; Ulf Schlichtmann (DATE, 2018)

Automated Redirection of Hardware Accesses for Host-Compiled Software Simulation. - Rafael Stahl; Daniel Mueller-Gritschneder; Ulf Schlichtmann (FDL, 2018)

Wavefront-MCTS: multi-objective design space exploration of NoC architectures based on Monte Carlo tree search. - Yong Hu; Daniel Mueller-Gritschneder; Ulf Schlichtmann (ICCAD, 2018)

Performance and accuracy in soft-error resilience evaluation using the multi-level processor simulator ETISS-ML. - Daniel Mueller-Gritschneder; Uzair Sharif; Ulf Schlichtmann (ICCAD, 2018)

Emulation of an ASIC Power, Temperature and Aging Monitor System for FPGA Prototyping. - Alexandra Listl; Daniel Mueller-Gritschneder; Fabian Kluge; Ulf Schlichtmann (IOLTS, 2018)

Efficient Fault Injection for Embedded Systems: As Fast as Possible but as Accurate as Necessary. - Petra R. Maier; Uzair Sharif; Daniel Mueller-Gritschneder; Ulf Schlichtmann (IOLTS, 2018)

Fault Injection for Test-Driven Development of Robust SoC Firmware. - Petra R. Maier; Veit B. Kleeberger; Daniel Mueller-Gritschneder; Ulf Schlichtmann (ACM Trans. Embed. Comput. Syst., 2018)

Graph-Grammar-Based IP-Integration (GRIP) - An EDA Tool for Software-Defined SoCs. - Munish Jassi; Yong Hu; Daniel Mueller-Gritschneder; Ulf Schlichtmann (ACM Trans. Design Autom. Electr. Syst., 2018)

SeRoHAL: generation of selectively robust hardware abstraction layers for efficient protection of mixed-criticality systems. - Petra R. Kleeberger; Juana Rivera; Daniel Mueller-Gritschneder; Ulf Schlichtmann (ASP-DAC, 2019)

Cross-Layer Resilience: Challenges, Insights, and the Road Ahead. - Eric Cheng; Daniel Mueller-Gritschneder; Jacob A. Abraham; Pradip Bose; Alper Buyuktosunoglu; Deming Chen; Hyungmin Cho; Yanjing Li; Uzair Sharif; Kevin Skadron; Mircea Stan; Ulf Schlichtmann; et al. (DAC, 2019)

ACCESS: HW/SW Co-Equivalence Checking for Firmware Optimization. - Michael Schwarz 010; Raphael Stahl; Daniel Müller-Gritschneder; Ulf Schlichtmann; Dominik Stoffel; Wolfgang Kunz (DAC, 2019)

Towards Reliable and Secure Post-Quantum Co-Processors based on RISC-V. - Tim Fritzmann; Uzair Sharif; Daniel Müller-Gritschneder; Cezar Reinbrecht; Ulf Schlichtmann; Johanna Sepúlveda (DATE, 2019)

SRAM Design Exploration with Integrated Application-Aware Aging Analysis. - Alexandra Listl; Daniel Mueller-Gritschneder; Ulf Schlichtmann; Sani R. Nassif (DATE, 2019)

MAGIC: A Wear-leveling Circuitry to Mitigate Aging Effects in Sense Amplifiers of SRAMs. - Alexandra Listl; Daniel Mueller-Gritschneder; Ulf Schlichtmann (NEWCAS, 2019)

Instruction Extension of a RISC-V Processor Modeled with IP-XACT. - Saman Payvar; Esko Pekkarinen; Rafael Stahl; Daniel Mueller-Gritschneder; Timo D. Hämäläinen (NORCAS, 2019)

Fully Distributed Deep Learning Inference on Resource-Constrained Edge Devices. - Rafael Stahl; Zhuoran Zhao 001; Daniel Mueller-Gritschneder; Andreas Gerstlauer; Ulf Schlichtmann (SAMOS, 2019)

Neural Network-based Vehicle Image Classification for IoT Devices. - Saman Payvar; Mir Khan; Rafael Stahl; Daniel Mueller-Gritschneder; Jani Boutellier (SiPS, 2019)

Analysis of Dissipative Losses in Modular Reconfigurable Energy Storage Systems Using SystemC TLM and SystemC-AMS. - Thomas Zimmermann 006; Mathias Mora; Sebastian Steinhorst; Daniel Mueller-Gritschneder; Andreas Jossen (ACM Trans. Design Autom. Electr. Syst., 2019)

Investigating the Inherent Soft Error Resilience of Embedded Applications by Full-System Simulation. - Uzair Sharif; Daniel Mueller-Gritschneder; Ulf Schlichtmann (ASP-DAC, 2020)

ML Training on a Tiny Microcontroller for a Self-adaptive Neural Network-Based DC Motor Speed Controller. - Frederik Funk; Thorsten Bucksch; Daniel Mueller-Gritschneder (IoT Streams/ITEM@PKDD/ECML, 2020)

Runtime Monitoring of Inter- and Intra-Thread Requirements on Embedded MPSoCs. - Marcel Mettler; Daniel Mueller-Gritschneder; Ulf Schlichtmann (VLSID, 2020)

Driver Generation for IoT Nodes With Optimization of the Hardware/Software Interface. - Rafael Stahl; Daniel Mueller-Gritschneder; Ulf Schlichtmann (IEEE Embed. Syst. Lett., 2020)

Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs. - Yong Hu; Marcel Mettler; Daniel Mueller-Gritschneder; Thomas Wild; Andreas Herkersdorf; Ulf Schlichtmann (ACM Trans. Design Autom. Electr. Syst., 2020)

Automated HW/SW co-design for edge AI: state, challenges and steps ahead. - Oliver Bringmann 001; Wolfgang Ecker; Ingo Feldner; Adrian Frischknecht; Christoph Gerum; Timo Hämäläinen 001; Muhammad Abdullah Hanif; Michael J. Klaiber; Daniel Mueller-Gritschneder; Paul Palomero Bernardo; Sebastian Siegfried Prebeck; Muhammad Shafique 001 (CODES+ISSS, 2021)

Tiny Generative Image Compression for Bandwidth-Constrained Sensor Applications. - Nikolai Körber; Andreas Siebert; Sascha Hauke; Daniel Mueller-Gritschneder (ICMLA, 2021)

Exploring the RISC-V Vector Extension for the Classic McEliece Post-Quantum Cryptosystem. - Sabine Pircher; Johannes Geier; Alexander Zeh; Daniel Mueller-Gritschneder (ISQED, 2021)

Learning based Memory Interference Prediction for Co-running Applications on Multi-Cores. - Ahsan Saeed; Daniel Mueller-Gritschneder; Falk Rehm; Arne Hamann 001; Dirk Ziegenbein; Ulf Schlichtmann; Andreas Gerstlauer (MLCAD, 2021)

DeeperThings: Fully Distributed CNN Inference on Resource-Constrained Edge Devices. - Rafael Stahl; Alexander Hoffman; Daniel Mueller-Gritschneder; Andreas Gerstlauer; Ulf Schlichtmann (Int. J. Parallel Program., 2021)

A Distributed Hardware Monitoring System for Runtime Verification on Multi-Tile MPSoCs. - Marcel Mettler; Daniel Mueller-Gritschneder; Ulf Schlichtmann (ACM Trans. Archit. Code Optim., 2021)

REPAIR: Control Flow Protection based on Register Pairing Updates for SW-Implemented HW Fault Tolerance. - Uzair Sharif; Daniel Mueller-Gritschneder; Ulf Schlichtmann (ACM Trans. Embed. Comput. Syst., 2021)

The Scale4Edge RISC-V Ecosystem. - Wolfgang Ecker; Peer Adelt; Wolfgang Müller 003; Reinhold Heckmann; Milos Krstic; Vladimir Herdt; Rolf Drechsler; Gerhard Angst; Ralf Wimmer 001; Andreas Mauderer; Rafael Stahl; Karsten Emrich; et al. (DATE, 2022)

CorePerfDSL: A Flexible Processor Description Language for Software Performance Simulation. - Conrad Foik; Daniel Mueller-Gritschneder; Ulf Schlichtmann (FDL, 2022)

COMPAS: Compiler-assisted Software-implemented Hardware Fault Tolerance for RISC-V. - Uzair Sharif; Daniel Mueller-Gritschneder; Ulf Schlichtmann (MECO, 2022)

Universal Safety Format: Automated Safety Software Generation. - Frederik Haxel; Alexander Viehl; Michael Benkel; Bjoern Beyreuther; Klaus Birken; Rolf Schmedes; Kim Grüttner; Daniel Mueller-Gritschneder (MODELSWARD, 2022)

Memory Utilization-Based Dynamic Bandwidth Regulation for Temporal Isolation in Multi-Cores. - Ahsan Saeed; Dakshina Dasari; Dirk Ziegenbein; Varun Rajasekaran; Falk Rehm; Michael Pressler; Arne Hamann 001; Daniel Mueller-Gritschneder; Andreas Gerstlauer; Ulf Schlichtmann (RTAS, 2022)

Key-Recovery Fault Injection Attack on the Classic McEliece KEM. - Sabine Pircher; Johannes Geier; Julian Danner; Daniel Mueller-Gritschneder; Antonia Wachter-Zeh (IACR Cryptol. ePrint Arch., 2022)

An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors. - Marcel Mettler; Martin Rapp; Heba Khdr; Daniel Mueller-Gritschneder; Jörg Henkel; Ulf Schlichtmann (ACM Trans. Archit. Code Optim., 2022)

CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V. - Johannes Geier; Lukas Auer; Daniel Mueller-Gritschneder; Uzair Sharif; Ulf Schlichtmann (ASP-DAC, 2023)

vRTLmod: An LLVM based Open-source Tool to Enable Fault Injection in Verilator RTL Simulations. - Johannes Geier; Daniel Mueller-Gritschneder (CF, 2023)

Towards Rapid Exploration of Heterogeneous TinyML Systems using Virtual Platforms and TVM's UMA. - Samira Ahmadifarsani; Rafael Stahl; Philipp van Kempen; Daniel Mueller-Gritschneder; Ulf Schlichtmann (CODAI, 2023)

MLonMCU: TinyML Benchmarking with Fast Retargeting. - Philipp van Kempen; Rafael Stahl; Daniel Mueller-Gritschneder; Ulf Schlichtmann (CODAI, 2023)

Extended Abstract: Monitoring-based Thermal Management for Mixed-Criticality Systems. - Marcel Mettler; Martin Rapp; Heba Khdr; Daniel Mueller-Gritschneder; Jörg Henkel; Ulf Schlichtmann (DATE, 2023)

Efficient Software-Implemented HW Fault Tolerance for TinyML Inference in Safety-critical Applications. - Uzair Sharif; Daniel Mueller-Gritschneder; Rafael Stahl; Ulf Schlichtmann (DATE, 2023)

Memory Latency Distribution-Driven Regulation for Temporal Isolation in MPSoCs. - Ahsan Saeed; Denis Hoornaert; Dakshina Dasari; Dirk Ziegenbein; Daniel Mueller-Gritschneder; Ulf Schlichtmann; Andreas Gerstlauer; Renato Mancuso 001 (ECRTS, 2023)

MonTM: Monitoring-Based Thermal Management for Mixed-Criticality Systems. - Marcel Mettler; Martin Rapp; Heba Khdr; Daniel Mueller-Gritschneder; Jörg Henkel; Ulf Schlichtmann (PARMA-DITAM, 2023)

Effective Processor Model Generation from Instruction Set Simulator to Hardware Design. - Johannes Kappes; Robert Kunzelmann; Karsten Emrich; Conrad Foik; Daniel Mueller-Gritschneder; Wolfgang Ecker (NorCAS, 2023)

Fused Depthwise Tiling for Memory Optimization in TinyML Deep Neural Network Inference. - Rafael Stahl; Daniel Mueller-Gritschneder; Ulf Schlichtmann (CoRR, 2023)

TinyProp - Adaptive Sparse Backpropagation for Efficient TinyML On-device Learning. - Marcus Rüb; Daniel Maier; Daniel Mueller-Gritschneder; Axel Sikora (CoRR, 2023)

EGIC: Enhanced Low-Bit-Rate Generative Image Compression Guided by Semantic Segmentation. - Nikolai Körber; Eduard Kromer; Andreas Siebert; Sascha Hauke; Daniel Mueller-Gritschneder (CoRR, 2023)

The Universal Safety Format in Action: Tool Integration and Practical Application. - Frederik Haxel; Alexander Viehl; Michael Benkel; Bjoern Beyreuther; Klaus Birken; Rolf Schmedes; Kim Grüttner; Daniel Mueller-Gritschneder (SN Comput. Sci., 2023)

muRISCV-NN: Challenging Zve32x Autovectorization with TinyML Inference Library for RISC-V Vector Extension. - Philipp van Kempen; Jefferson Parker Jones; Daniel Mueller-Gritschneder; Ulf Schlichtmann (CF (Companion), 2024)

MuDSE: GA-ILP-based Framework for Automated Deployment of Multiple DNNs on Heterogeneous Mixed-Criticality Systems. - Alexander Hoffman; Ala Fnayou; Fedor Smirnov; Daniel Mueller-Gritschneder; Ulf Schlichtmann (COINS, 2024)

MATAR: Multi-Quantization-Aware Training for Accurate and Fast Hardware Retargeting. - Pierpaolo Morì; Moritz Thoma; Lukas Frickenstein; Shambhavi Balamuthu Sampath; Nael Fasfous; Manoj Rohit Vemparala; Alexander Frickenstein; Walter Stechele; Daniel Mueller-Gritschneder; Claudio Passerone (DATE, 2024)

Seal5: Semi-Automated LLVM Support for RISC-V ISA Extensions Including Autovectorization. - Philipp van Kempen; Mathis Salmen; Daniel Mueller-Gritschneder; Ulf Schlichtmann (DSD, 2024)

EGIC: Enhanced Low-Bit-Rate Generative Image Compression Guided by Semantic Segmentation. - Nikolai Körber; Eduard Kromer; Andreas Siebert; Sascha Hauke; Daniel Mueller-Gritschneder; Björn W. Schuller (ECCV (35), 2024)

Energy-Aware Speed Regulation in Electrical Drives: A Load-Agnostic Motor Control Approach via Reinforcement Learning. - Steven Klotz; Thorsten Bucksch; Dip Goswami; Daniel Mueller-Gritschneder (ECC, 2024)

A Continual and Incremental Learning Approach for TinyML On-device Training Using Dataset Distillation and Model Size Adaption. - Marcus Rüb; Philipp Tuchel; Axel Sikora; Daniel Mueller-Gritschneder (ICPS, 2024)

Advancing On-Device Neural Network Training with TinyPropv2: Dynamic, Sparse, and Efficient Backpropagation. - Marcus Rüb; Axel Sikora; Daniel Mueller-Gritschneder (IJCNN, 2024)

MuNAS: TinyML Network Architecture Search Using Goal Attainment and Reinforcement Learning. - Alexander Hoffman; Ulf Schlichtmann; Daniel Mueller-Gritschneder (MECO, 2024)

Wino Vidi Vici: Conquering Numerical Instability of 8-bit Winograd Convolution for Accurate Inference Acceleration on Edge. - Pierpaolo Morì; Lukas Frickenstein; Shambhavi Balamuthu Sampath; Moritz Thoma; Nael Fasfous; Manoj Rohit Vemparala; Alexander Frickenstein; Christian Unger; Walter Stechele; Daniel Mueller-Gritschneder; Claudio Passerone (WACV, 2024)

PerCo (SD): Open Perceptual Compression. - Nikolai Körber; Eduard Kromer; Andreas Siebert; Sascha Hauke; Daniel Mueller-Gritschneder; Björn W. Schuller (CoRR, 2024)

Flexible Generation of Fast and Accurate Software Performance Simulators From Compact Processor Descriptions. - Conrad Foik; Robert Kunzelmann; Daniel Mueller-Gritschneder; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Uncertainty Aware Training to Improve Uncertainty Active Learning for Semantic Segmentation. - Moritz Thoma; Tobias Preintner; Emad Aghajanzadeh; Shambhavi Balamuthu Sampath; Pierpaolo Morì; Nael Fasfous; Manoj Rohit Vemparala; Alexander Frickenstein; Daniel Mueller-Gritschneder; Ulf Schlichtmann (CVPR Workshops, 2025)

FLAR-SVD: Fast and Latency-Aware Singular Value Decomposition for Model Compression. - Moritz Thoma; Jorge Villasante; Emad Aghajanzadeh; Shambhavi Balamuthu Sampath; Pierpaolo Morì; Maximilian Groetzinger; Daniil Dylkin; Manoj Rohit Vemparala; Nael Fasfous; Alexander Frickenstein; Daniel Mueller-Gritschneder; Ulf Schlichtmann (CVPR Workshops, 2025)

Rapid Fault Injection Simulation by Hash-Based Differential Fault Effect Equivalence Checks. - Johannes Geier; Leonidas Kontopoulos; Daniel Mueller-Gritschneder; Ulf Schlichtmann (DATE, 2025)

HiFi-SAGE: High Fidelity GraphSAGE-Based Latency Estimators for DNN Optimization. - Shambhavi Balamuthu Sampath; Leon Hecht; Moritz Thoma; Lukas Frickenstein; Pierpaolo Morì; Nael Fasfous; Manoj Rohit Vemparala; Alexander Frickenstein; Walter Stechele; Daniel Mueller-Gritschneder; Claudio Passerone (DATE, 2025)

PerCoV2: Improved Ultra-Low Bit-Rate Perceptual Image Compression with Implicit Hierarchical Masked Image Modeling. - Nikolai Körber; Eduard Kromer; Andreas Siebert; Sascha Hauke; Daniel Mueller-Gritschneder; Björn W. Schuller (CoRR, 2025)

DRIP: DRop unImportant data Points - Enhancing Machine Learning Efficiency with Grad-CAM-Based Real-Time Data Prioritization for On-Device Training. - Marcus Rüb; Daniel Konegen; Axel Sikora; Daniel Mueller-Gritschneder (CoRR, 2025)

A High-Level Compiler Integration Approach for Deep Learning Accelerators Supporting Abstraction and Optimization. - Samira Ahmadifarsani; Daniel Mueller-Gritschneder; Ulf Schlichtmann (CoRR, 2025)