Daniel Palomino
Orcid: 0000-0003-0409-8335Affiliations:
- Federal University of Pelotas, RS, Brazil
- Federal University of Rio Grande do Sul, Porto Alegre, RS, Brazil (PhD 2013)
According to our database1,
Daniel Palomino
authored at least 75 papers
between 2009 and 2023.
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Bibliography
2023
IEEE Des. Test, October, 2023
A Machine Learning-Based Solution to Accelerate the Intra Mode Decision for the VVC Standard.
Proceedings of the 29th Brazilian Symposium on Multimedia and the Web, 2023
A Hardware Design for the Multi-Transform Module of the Versatile Video Coding Standard.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023
Error Resilience Evaluation of Approximate Storage in the Motion Compensation of VVC Decoders.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
Fast Intra Mode Decision Using Machine Learning for the Versatile Video Coding Standard.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the 31st European Signal Processing Conference, 2023
2022
IEEE Trans. Circuits Syst. Video Technol., 2022
Power-Quality Configurable Hardware Design for AV1 Directional Intraframe Prediction.
IEEE Des. Test, 2022
Proceedings of the WebMedia '22: Brazilian Symposium on Multimedia and Web, Curitiba, Brazil, November 7, 2022
Full Reference Stereoscopic Objective Quality Assessment using Lightweight Machine Learning.
Proceedings of the WebMedia '22: Brazilian Symposium on Multimedia and Web, Curitiba, Brazil, November 7, 2022
Error Resilience Evaluation of Approximate Storage in the Intra Prediction of VVC Decoders.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Multiple Transform Selection Hardware Design for 4K@60fps Real-Time Versatile Video Coding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Fast Affine Motion Estimation for VVC using Machine-Learning-Based Early Search Termination.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 2022 IEEE International Conference on Image Processing, 2022
2021
IEEE Open J. Circuits Syst., 2021
Exploring Operation Sharing in Directional Intra Frame Prediction of AV1 Video Coding.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
2020
6WR: A Hardware Friendly 3D-HEVC DMM-1 Algorithm and its Energy-Aware and High-Throughput Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
J. Real Time Image Process., 2020
Power/QoS-Adaptive HEVC FME Hardware using Machine Learning-Based Approximation Control.
Proceedings of the 2020 IEEE International Conference on Visual Communications and Image Processing, 2020
Proceedings of the 2020 IEEE International Conference on Visual Communications and Image Processing, 2020
Proceedings of the 2020 IEEE International Conference on Visual Communications and Image Processing, 2020
Directional Intra Frame Prediction Architecture with Edge Filter and Upsampling for AV1 Video Coding.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Low-Power and Memory-Aware Approximate Hardware Architecture for Fractional Motion Estimation Interpolation on HEVC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
ASIC Solution for the Directional Intra Prediction of the AV1 Encoder Targeting UHD 4K Videos.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
An Overview of Dedicated Hardware Designs for State-of-the-Art AV1 and H.266/VVC Video Codecs.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
RDE-MOGA: Automatic Selection of Rate-Distortion-Energy Control Points for Video Encoders Using Muti-Objetive Genetic Algorithm.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Proceedings of the 28th European Signal Processing Conference, 2020
Proceedings of the 28th European Signal Processing Conference, 2020
Proceedings of the 28th European Signal Processing Conference, 2020
Proceedings of the 28th European Signal Processing Conference, 2020
2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Performance evaluation of HEVC RCL applications mapped onto NoC-based embedded platforms.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019
Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Encoding Efficiency and Computational Cost Assessment of State-Of-The-Art Point Cloud Codecs.
Proceedings of the 2019 IEEE International Conference on Image Processing, 2019
Energy-Efficiency Exploration of Memory Hierarchy using NVMs for HEVC Motion Estimation.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
A New Hardware Friendly 2D-DCT HEVC Compliant Algorithm and its High Throughput and Low Power Hardware Design.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
A Fast Local Mode Decision for the HEVC Intra Prediction Based on Direction Detection.
Proceedings of the 27th European Signal Processing Conference, 2019
Compression Efficiency and Computational Cost Comparison between AV1 and HEVC Encoders.
Proceedings of the 27th European Signal Processing Conference, 2019
Proceedings of the Data Compression Conference, 2019
Proceedings of the Data Compression Conference, 2019
2018
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
High-Throughput and Low-Power Integrated Direct/Inverse HEVC Quantization Hardware Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Memory-Aware Tiles Workload Balance through Machine-Learnt Complexity Reduction for HEVC.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Power-Efficient and Memory-Aware Approximate Hardware Design for HEVC FME Interpolator.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
2017
Proceedings of the VII Brazilian Symposium on Computing Systems Engineering, 2017
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
2016
Adjusting video tiling to available resources in a per-frame basis in High Efficiency Video Coding.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2014
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
hevcDTM: Application-driven Dynamic Thermal Management for High Efficiency Video Coding.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Fast HEVC intra mode decision algorithm based on new evaluation order in the Coding Tree Block.
Proceedings of the 30th Picture Coding Symposium, 2013
Proceedings of the 30th Picture Coding Symposium, 2013
2012
Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder.
VLSI Design, 2012
Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders.
Int. J. Reconfigurable Comput., 2012
A memory aware and multiplierless VLSI architecture for the complete Intra Prediction of the HEVC emerging standard.
Proceedings of the 19th IEEE International Conference on Image Processing, 2012
2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
SHBS: A heuristic for fast inter mode decision of H.264/AVC standard targeting VLSI design.
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011
2010
High Throughput and Low Cost Architecture for the Forward Quantization of the H.264/AVC Video Compression Standard.
CLEI Electron. J., 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2009
Transforms and quantization design targeting the H.264/AVC intra prediction constraints.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
Low latency and high throughput dedicated loop of transforms and quantization focusing in the H.264/AVC Intra Prediction.
Proceedings of the International Conference on Image Processing, 2009
A multitransform architecture for the H.264/AVC standard and its design space exploration.
Proceedings of the 16th IEEE International Conference on Electronics, 2009