Daniel Palomino

According to our database1, Daniel Palomino authored at least 35 papers between 2009 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
High-Throughput Multifilter Interpolation Architecture for AV1 Motion Compensation.
IEEE Trans. on Circuits and Systems, 2019

Performance evaluation of HEVC RCL applications mapped onto NoC-based embedded platforms.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

Advanced Transfer Learning Approach for Improving Spanish Sentiment Analysis.
Proceedings of the Advances in Soft Computing, 2019

Low-Power and High-Throughput Approximate 4×4 DCT Hardware Architecture.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

A High Throughput Hardware Architecture Targeting the AV1 Paeth Intra Predictor.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

High Throughput Hardware Design for AV1 Paeth and Smooth Intra Modes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Fast Local Mode Decision for the HEVC Intra Prediction Based on Direction Detection.
Proceedings of the 27th European Signal Processing Conference, 2019

Compression Efficiency and Computational Cost Comparison between AV1 and HEVC Encoders.
Proceedings of the 27th European Signal Processing Conference, 2019

FastIntra360: A Fast Intra-Prediction Technique for 360-Degrees Video Coding.
Proceedings of the Data Compression Conference, 2019

Online Machine Learning for Fast Coding Unit Decisions in HEVC.
Proceedings of the Data Compression Conference, 2019

2018
Low-Power HEVC 1-D IDCT Hardware Architecture.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Configurable Cache Memory Architecture for Low-Energy Motion Estimation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

OTED: Encoding Optimization Technique Targeting Energy-Efficient HEVC Decoding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

High-Throughput and Low-Power Integrated Direct/Inverse HEVC Quantization Hardware Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Memory-Aware Tiles Workload Balance through Machine-Learnt Complexity Reduction for HEVC.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Power-Efficient and Memory-Aware Approximate Hardware Design for HEVC FME Interpolator.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Cache Memory Energy Efficiency Exploration for the HEVC Motion Estimation.
Proceedings of the VII Brazilian Symposium on Computing Systems Engineering, 2017

Energy evaluation of the HEVC decoding for different encoding configurations.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

2016
Adjusting video tiling to available resources in a per-frame basis in High Efficiency Video Coding.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Speedup-aware history-based tiling algorithm for the HEVC standard.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

Thermal optimization using adaptive approximate computing for video coding.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2014
TONE: adaptive temperature optimization for the next generation video encoders.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

hevcDTM: Application-driven Dynamic Thermal Management for High Efficiency Video Coding.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Fast HEVC intra mode decision algorithm based on new evaluation order in the Coding Tree Block.
Proceedings of the 30th Picture Coding Symposium, 2013

Adaptive content-based Tile partitioning algorithm for the HEVC standard.
Proceedings of the 30th Picture Coding Symposium, 2013

2012
Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder.
VLSI Design, 2012

Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders.
Int. J. Reconfig. Comp., 2012

A memory aware and multiplierless VLSI architecture for the complete Intra Prediction of the HEVC emerging standard.
Proceedings of the 19th IEEE International Conference on Image Processing, 2012

2011
A high throughput H.264/AVC intra-frame encoding loop architecture for HD1080p.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

SHBS: A heuristic for fast inter mode decision of H.264/AVC standard targeting VLSI design.
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011

2010
High Throughput and Low Cost Architecture for the Forward Quantization of the H.264/AVC Video Compression Standard.
CLEI Electron. J., 2010

Homogeneity and distortion-based intra mode decision architecture for H.264/AVC.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
Transforms and quantization design targeting the H.264/AVC intra prediction constraints.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Low latency and high throughput dedicated loop of transforms and quantization focusing in the H.264/AVC Intra Prediction.
Proceedings of the International Conference on Image Processing, 2009

A multitransform architecture for the H.264/AVC standard and its design space exploration.
Proceedings of the 16th IEEE International Conference on Electronics, 2009


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