Die Stacking (3D) Microarchitecture. - Bryan Black; Murali Annavaram; Ned Brekelbaum; John DeVale; Lei Jiang; Gabriel H. Loh; Don McCaule; Patrick Morrow; Donald W. Nelson; Daniel Pantuso; Paul Reed; Jeff Rupley; et al. (MICRO, 2006)

Silicon Reliability Characterization of Intel's Foveros 3D Integration Technology for Logic-on-Logic Die Stacking. - Chetan Prasad; Sunny Chugh; Hannes Greve; I-chen Ho; Enamul Kabir; Cheyun Lin; Mahjabin Maksud; Steven R. Novak; Benjamin Orr; Keun Woo Park; Anthony Schmitz; Zhizheng Zhang 006; et al. (IRPS, 2020)

Localized thermal effects in Gate-all-around devices. - Colin Landon; Lei Jiang; Daniel Pantuso; Inanc Meric; Kam Komeyli; Jeffrey Hicks; Daniel Schroeder (IRPS, 2023)