Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor. - Leon J. Sigal; James D. Warnock; Brian W. Curran; Yuen H. Chan; Peter J. Camporese; Mark D. Mayo; William V. Huott; Daniel R. Knebel; Ching-Te Chuang; James P. Eckhardt; Philip T. Wu (IBM J. Res. Dev., 1997)

Diagnosis and characterization of timing-related defects by time-dependent light emission. - Daniel R. Knebel; Pia N. Sanda; Moyra K. McManus; Jeffrey A. Kash; James C. Tsang; David P. Vallett; Leendert M. Huisman; Phil Nigh; Rick Rizzolo; Peilin Song; Franco Motika (ITC, 1998)

The attack of the "Holey Shmoos": a case study of advanced DFD and picosecond imaging circuit analysis (PICA). - William V. Huott; Moyra K. McManus; Daniel R. Knebel; Steve Steen; Dennis Manzer; Pia N. Sanda; Steven C. Wilson; Yuen H. Chan; Antonio Pelella; Stanislav Polonsky (ITC, 1999)

Diagnostic techniques for the IBM S/390 600 MHz G5 microprocessor. - Peilin Song; Franco Motika; Daniel R. Knebel; Rick Rizzolo; Mary P. Kusko; Julie Lee; Moyra K. McManus (ITC, 1999)

S/390 G5 CMOS microprocessor diagnostics. - Peilin Song; Franco Motika; Daniel R. Knebel; Richard F. Rizzolo; Mary P. Kusko (IBM J. Res. Dev., 1999)

Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis. - Stanislav Polonsky; Moyra K. McManus; Daniel R. Knebel; Steve Steen; Pia N. Sanda (Asian Test Symposium, 2000)

Minimizing inductive noise in system-on-a-chip with multiple power gating structures. - Suhwan Kim 001; Stephen V. Kosonocky; Daniel R. Knebel; Kevin Stawiasz; David F. Heidel; Michael Immediato (ESSCIRC, 2003)

Understanding and minimizing ground bounce during mode transition of power gating structures. - Suhwan Kim 001; Stephen V. Kosonocky; Daniel R. Knebel (ISLPED, 2003)

Low-power circuits and technology for wireless digital systems. - Stephen V. Kosonocky; Azeez J. Bhavnagarwala; Kenneth Chin; George Gristede; Anne-Marie Haen; Wei Hwang; Mark B. Ketchen; Suhwan Kim 001; Daniel R. Knebel; Kevin W. Warren; Victor V. Zyuban (IBM J. Res. Dev., 2003)

Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits. - Jean-Olivier Plouchart; Noah Zamdmer; Jonghae Kim; Melanie Sherony; Yue Tan; Asit Ray; Mohamed Talbi; Lawrence F. Wagner; Kun Wu; Naftali E. Lustig; Shreesh Narasimha; Patricia O'Neil; et al. (IBM J. Res. Dev., 2003)

Experimental measurement of a novel power gating structure with intermediate power saving mode. - Suhwan Kim 001; Stephen V. Kosonocky; Daniel R. Knebel; Kevin Stawiasz (ISLPED, 2004)

A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs. - Suhwan Kim 001; Stephen V. Kosonocky; Daniel R. Knebel; Kevin Stawiasz; Marios C. Papaefthymiou (IEEE Trans. Circuits Syst. II Express Briefs, 2007)