Dynamic hit logic with embedded 8Kb SRAM in 45nm SOI for the zEnterprise™ processor. - Antonio Pelella; Yuen H. Chan; Bargav Balakrishnan; Pradip Patel; Daniel Rodko; Richard E. Serton (ISSCC, 2011)

Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System. - James D. Warnock; Yiu-Hing Chan; Sean M. Carey; Huajun Wen; Patrick J. Meaney; Guenter Gerwig; Howard H. Smith; Yuen H. Chan; John Davis; Paul Bunce; Antonio Pelella; Daniel Rodko; et al. (IEEE J. Solid State Circuits, 2012)

7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor. - John Davis; Paul Bunce; Diana M. Henderson; Yuen H. Chan; Uma Srinivasan 002; Daniel Rodko; Pradip Patel; Thomas J. Knips; Tobias Werner 001 (ISSCC, 2013)