REPAS: Reliable Execution for Parallel ApplicationS in Tiled-CMPs. - Daniel Sánchez 004; Juan L. Aragón; José M. García 001 (Euro-Par, 2009)

Extending SRT for parallel applications in tiled-CMP architectures. - Daniel Sánchez 004; Juan L. Aragón; José M. García 001 (IPDPS, 2009)

A log-based redundant architecture for reliable parallel computation. - Daniel Sánchez 004; Juan L. Aragón; José M. García 001 (HiPC, 2010)

An analytical model for the calculation of the Expected Miss Ratio in faulty caches. - Daniel Sánchez 004; Yiannakis Sazeides; Juan L. Aragón; José M. García 001 (IOLTS, 2011)

A fault-tolerant architecture for parallel applications in tiled-CMPs. - Daniel Sánchez 004; Juan L. Aragón; José M. García 001 (J. Supercomput., 2012)

Efficient inter-core power and thermal balancing for multicore processors. - Juan M. Cebrian; Daniel Sánchez 004; Juan L. Aragón; Stefanos Kaxiras (Computing, 2013)

Modeling the impact of permanent faults in caches. - Daniel Sánchez 004; Yiannakis Sazeides; Juan M. Cebrian; José M. García 001; Juan L. Aragón (ACM Trans. Archit. Code Optim., 2013)

Managing power constraints in a single-core scenario through power tokens. - Juan M. Cebrian; Daniel Sánchez 004; Juan L. Aragón; Stefanos Kaxiras (J. Supercomput., 2014)

Soft-error mitigation by means of decoupled transactional memory threads. - Daniel Sánchez 004; Juan M. Cebrian; José M. García 001; Juan L. Aragón (Distributed Comput., 2015)