Reducing quantization noise with recursive Sigma Delta modulators. - Daniël Schinkel; Ed van Tuijl; Anne-Johan Annema (ISCAS (1), 2004)

An audio FIR-DAC in a BCD process for high power class-D amplifiers. - T. S. Doorn; Ed van Tuijl; Daniël Schinkel; Anne-Johan Annema; Marco Berkhout; Bram Nauta (ESSCIRC, 2005)

Optimally-placed twists in global on-chip differential interconnects. - Eisse Mensink; Daniël Schinkel; Eric A. M. Klumperink; Ed van Tuijl; Bram Nauta (ESSCIRC, 2005)

A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects. - Daniël Schinkel; Eisse Mensink; Eric A. M. Klumperink; Ed J. M. van Tuijl; Bram Nauta (IEEE J. Solid State Circuits, 2006)

A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects. - Eisse Mensink; Daniël Schinkel; Eric A. M. Klumperink; Ed van Tuijl; Bram Nauta (ISSCC, 2007)

A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time. - Daniël Schinkel; Eisse Mensink; Eric A. M. Klumperink; Ed van Tuijl; Bram Nauta (ISSCC, 2007)

Optimal Positions of Twists in Global On-Chip Differential Interconnects. - Eisse Mensink; Daniël Schinkel; Eric A. M. Klumperink; Ed van Tuijl; Bram Nauta (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC. - Michiel van Elzakker; Ed van Tuijl; Paul F. J. Geraedts; Daniël Schinkel; Eric A. M. Klumperink; Bram Nauta (ISSCC, 2008)

Low-Power, High-Speed Transceivers for Network-on-Chip Communication. - Daniël Schinkel; Eisse Mensink; Eric A. M. Klumperink; Ed van Tuijl; Bram Nauta (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A 10-bit Charge-Redistribution ADC Consuming 1.9 μ W at 1 MS/s. - Michiel van Elzakker; Ed van Tuijl; Paul F. J. Geraedts; Daniël Schinkel; Eric A. M. Klumperink; Bram Nauta (IEEE J. Solid State Circuits, 2010)

Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects. - Eisse Mensink; Daniël Schinkel; Eric A. M. Klumperink; Ed van Tuijl; Bram Nauta (IEEE J. Solid State Circuits, 2010)

15.3 A 115dB-DR audio DAC with -61dBFS out-of-band noise. - Hugo Westerveld; Daniël Schinkel; Ed van Tuijl (ISSCC, 2015)

5.1 A 5×80W 0.004% THD+N automotive multiphase Class-D audio amplifier with integrated low-latency ΔΣ ADCs for digitized feedback after the output filter. - Fred Mostert; Daniël Schinkel; Wouter Groothedde; Lucien J. Breems; Remko van Heeswijk; Marto-Jan Koerts; Eric van Iersel; Daniel Groeneveld; Gertjan van Holland; Patrick Zeelen; Derk-Jan Hissink; Martin Pos; et al. (ISSCC, 2017)

A Multiphase Class-D Automotive Audio Amplifier With Integrated Low-Latency ADCs for Digitized Feedback After the Output Filter. - Daniël Schinkel; Wouter Groothedde; Fred Mostert; Marto-Jan Koerts; Eric van Iersel; Daniel Groeneveld; Lucien J. Breems (IEEE J. Solid State Circuits, 2017)

A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise. - Harijot Singh Bindra; Chris E. Lokin; Daniël Schinkel; Anne-Johan Annema; Bram Nauta (IEEE J. Solid State Circuits, 2018)

EMI Reduction in Class-D Amplifiers by Actively Reducing PWM Ripple. - Christiaan E. Lokin; Ronan A. R. van der Zee; Daniël Schinkel; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Compensating Processing Delay in Excess of One Clock Cycle in Noise Shaping Loops Without Altering the Filter Topology. - Christiaan E. Lokin; Daniël Schinkel; Ronan A. R. van der Zee; Bram Nauta (IEEE Access, 2021)