Daniel W. Storaska

According to our database, Daniel W. Storaska authored at least 9 papers between 1999 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS.

Gautam Reddy Gangasani, D. Hanson, Daniel W. Storaska, H. H. Xu, M. Kelly, M. Shannon, Michael Sorna, Michael Wielgos, P. B. Ramakrishna, S. Shi, S. Parker, U. K. Shukla, W. Kelly, W. Su, Z. Yu

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2014

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.

Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Troy J. Beukema, William Kelly, Hui H. Xu, David Freitas, Andrea Prati, Daniele Gardellini, Robert Reutemann, Giovanni Cervelli, Juergen Hertle, Matthew Baecher, Jon Garlett, Pier Andrea Francese, John F. Ewen, David Hanson, Daniel W. Storaska, Mounir Meghelli

IEEE J. Solid State Circuits, 2014

2012

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology.

John F. Bulzacchelli, Christian Menolfi, Troy J. Beukema, Daniel W. Storaska, Juergen Hertle, David Hanson, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, W. R. Kelly, L. R. Chieco, Glenn Ritter, J. A. Sorice, Jon Garlett, Robert Callan, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Toifl, Daniel J. Friedman

IEEE J. Solid State Circuits, 2012

A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology.

John F. Bulzacchelli, Troy J. Beukema, Daniel W. Storaska, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Christian Menolfi, David Hanson, Juergen Hertle, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William Kelly, Glenn Ritter, Jon Garlett, Robert Callan, Thomas Toifl, Daniel J. Friedman

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2005

10+ gb/s 90-nm CMOS serial link demo in CBGA package.

Sergey V. Rylov, Scott K. Reynolds, Daniel W. Storaska, Brian A. Floyd, Mohit Kapur, Thomas Zwick, Sudhir M. Gowda, Michael Sorna

IEEE J. Solid State Circuits, 2005

2004

10+ Gb/s 90nm CMOS serial link demo in CBGA package.

Sergey V. Rylov, Scott K. Reynolds, Daniel W. Storaska, Brian A. Floyd, Mohit Kapur, Thomas Zwick, Sudhir M. Gowda, Michael Sorna

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2000

Advanced controlling scheme for a DRAM voltage generator system.

Oliver Weinfurtner, Daniel W. Storaska, Louis Hsu

IEEE J. Solid State Circuits, 2000

A 7F² cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs.

Heinz Hoenigschmid, Alexander Frey, John K. DeBrosse, Toshiaki Kirihata, Gerhard Mueller, Daniel W. Storaska, Gabriel Daniel, Gerd Frankowsky, Kevin P. Guay, David R. Hanson, Louis Lu-Chen Hsu, Brian Ji, Dmitry G. Netis, Steve Panaroni, Carl Radens, Armin M. Reith, Hartmud Terletzki, Oliver Weinfurtner, Johann Alsmeier, Werner Weber, Matthew R. Wordeman

IEEE J. Solid State Circuits, 2000

1999

A 390-mm², 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture.

Toshiaki Kirihata, Gerhard Mueller, Brian Ji, Gerd Frankowsky, John M. Ross, Hartmud Terletzki, Dmitry G. Netis, Oliver Weinfurtner, David R. Hanson, Gabriel Daniel, Louis Lu-Chen Hsu, Daniel W. Storaska, Armin M. Reith, Marco A. Hug, Kevin P. Guay, Manfred Selz, Peter Poechmueller, Heinz Hoenigschmid, Matthew R. Wordeman

IEEE J. Solid State Circuits, 1999