Optimizing performance analysis for synchronous dataflow graphs with shared resources. - Daniel Thiele; Rolf Ernst (DATE, 2012)

Formal worst-case timing analysis of Ethernet topologies with strict-priority and AVB switching. - Jonas Diemer; Daniel Thiele; Rolf Ernst (SIES, 2012)

Improved formal worst-case timing analysis of weighted round robin scheduling for Ethernet. - Daniel Thiele; Jonas Diemer; Philip Axer; Rolf Ernst; Jan R. Seyler (CODES+ISSS, 2013)

Improving formal timing analysis of switched ethernet by exploiting traffic stream correlations. - Daniel Thiele; Philip Axer; Rolf Ernst; Jan R. Seyler (CODES+ISSS, 2014)

Exploiting Shaper Context to Improve Performance Bounds of Ethernet AVB Networks. - Philip Axer; Daniel Thiele; Rolf Ernst; Jonas Diemer (DAC, 2014)

Formal timing analysis of automatic repeat request for switched real-time networks. - Philip Axer; Daniel Thiele; Rolf Ernst (SIES, 2014)

Improving formal timing analysis of switched ethernet by exploiting FIFO scheduling. - Daniel Thiele; Philip Axer; Rolf Ernst (DAC, 2015)

Formal worst-case timing analysis of Ethernet TSN's time-aware and peristaltic shapers. - Daniel Thiele; Rolf Ernst; Jonas Diemer (VNC, 2015)

Invited - Towards fail-operational ethernet based in-vehicle networks. - Mischa Möstl; Daniel Thiele; Rolf Ernst (DAC, 2016)

Formal analysis based evaluation of software defined networking for time-sensitive Ethernet. - Daniel Thiele; Rolf Ernst (DATE, 2016)

Formal worst-case timing analysis of Ethernet TSN's burst-limiting shaper. - Daniel Thiele; Rolf Ernst (DATE, 2016)

Formal worst-case performance analysis of time-sensitive Ethernet with frame preemption. - Daniel Thiele; Rolf Ernst (ETFA, 2016)

Formal timing analysis of CAN-to-Ethernet gateway strategies in automotive networks. - Daniel Thiele; Johannes Schlatow; Philip Axer; Rolf Ernst (Real Time Syst., 2016)

A system-level FPGA design methodology for video applications with weakly-programmable hardware components. - Henning Sahlbach; Daniel Thiele; Rolf Ernst (J. Real Time Image Process., 2017)

Networked Real-Time Embedded Systems. - Haibo Zeng 001; Prachi Joshi; Daniel Thiele; Jonas Diemer; Philip Axer; Rolf Ernst; Petru Eles (Handbook of Hardware/Software Codesign, 2017)

Formal Timing Analysis of Ethernet TSN Extensions for Automotive Applications (Formale Timing Analyse von Ethernet TSN Erweiterungen für automobile Anwendungen) - Daniel Thiele (2022)