A 390-mm2, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture. - Toshiaki Kirihata; Gerhard Mueller; Brian Ji; Gerd Frankowsky; Joseph M. Ross; Hartmud Terletzki; Dmitry G. Netis; Oliver Weinfurtner; David R. Hanson; Gabriel Daniel; Louis Lu-Chen Hsu; Daniel W. Storaska; et al. (IEEE J. Solid State Circuits, 1999)

A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs. - Heinz Hoenigschmid; Alexander Frey; John K. DeBrosse; Toshiaki Kirihata; Gerhard Mueller; Daniel W. Storaska; Gabriel Daniel; Gerd Frankowsky; Kevin P. Guay; David R. Hanson; Louis Lu-Chen Hsu; Brian Ji; et al. (IEEE J. Solid State Circuits, 2000)

Advanced controlling scheme for a DRAM voltage generator system. - Oliver Weinfurtner; Daniel W. Storaska; Louis Hsu (IEEE J. Solid State Circuits, 2000)

10+ Gb/s 90nm CMOS serial link demo in CBGA package. - Sergey V. Rylov; Scott K. Reynolds; Daniel W. Storaska; Brian A. Floyd; Mohit Kapur; Thomas Zwick; Sudhir M. Gowda; Michael Sorna (CICC, 2004)

10+ gb/s 90-nm CMOS serial link demo in CBGA package. - Sergey V. Rylov; Scott K. Reynolds; Daniel W. Storaska; Brian A. Floyd; Mohit Kapur; Thomas Zwick; Sudhir M. Gowda; Michael Sorna (IEEE J. Solid State Circuits, 2005)

A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology. - John F. Bulzacchelli; Troy J. Beukema; Daniel W. Storaska; Ping-Hsuan Hsieh; Sergey V. Rylov; Daniel Furrer; Daniele Gardellini; Andrea Prati 002; Christian Menolfi; David Hanson; Juergen Hertle; Thomas Morf; et al. (ISSCC, 2012)

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. - John F. Bulzacchelli; Christian Menolfi; Troy J. Beukema; Daniel W. Storaska; Juergen Hertle; David Hanson; Ping-Hsuan Hsieh; Sergey V. Rylov; Daniel Furrer; Daniele Gardellini; Andrea Prati 002; Thomas Morf; et al. (IEEE J. Solid State Circuits, 2012)

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Troy J. Beukema; William R. Kelly; Hui H. Xu; David Freitas; Andrea Prati 002; Daniele Gardellini; Robert Reutemann; Giovanni Cervelli; Juergen Hertle; et al. (IEEE J. Solid State Circuits, 2014)

A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS. - Gautam Reddy Gangasani; D. Hanson; Daniel W. Storaska; H. H. Xu; M. Kelly; M. Shannon; Michael Sorna; Michael Wielgos; P. B. Ramakrishna; S. Shi; S. Parker; U. K. Shukla; et al. (ISSCC, 2022)

A 1.1pJ/b/Lane, 1.8Tb/s Chiplet Over XSR-MCM Channels Using 113Gb/s PAM-4 Transceiver with Signal Equalization and Envelope Adaptation Using TX-FFE in 5nm CMOS. - Gautam R. Gangasani; A. Mostafa; A. Singh; Daniel W. Storaska; D. Prabakaran; K. Mohammad; Matthew Baecher; M. Shannon; Michael Sorna; Michael Wielgos; P. Jenkins; P. B. Ramakrishna; et al. (VLSI Technology and Circuits, 2024)

7.2: A 2.2pJ/b 212.5Gb/s PAM-4 Transceiver with >46dB Reach in 5nm FinFET. - Ahmed Mostafa; A. Hassan; A. Hsu; A. K. Singh; C.-H. Wu; C.-R. Yang; D. Prabakaran; Daniel W. Storaska; D. Zhou; Davide Visani; Edmund Hsiao; F. Chu; et al. (ISSCC, 2025)