Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. - Daniel Ziener; Stefan Assmus; Jürgen Teich (FPL, 2006)

FPGA core watermarking based on power signature analysis. - Daniel Ziener; Jürgen Teich (FPT, 2006)

Concepts for Autonomous Control Flow Checking for Embedded CPUs. - Daniel Ziener; Jürgen Teich (ATC, 2008)

Netlist-level IP protection by watermarking for LUT-based FPGAs. - Moritz Schmid; Daniel Ziener; Jürgen Teich (FPT, 2008)

Power Signature Watermarking of IP Cores for FPGAs. - Daniel Ziener; Jürgen Teich (J. Signal Process. Syst., 2008)

Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs. - Daniel Ziener; Jürgen Teich (Int. J. Auton. Adapt. Commun. Syst., 2009)

New Directions for IP Core Watermarking and Identification. - Daniel Ziener; Jürgen Teich (Dynamically Reconfigurable Architectures, 2010)

A rapid prototyping system for error-resilient multi-processor systems-on-chip. - Matthias May 001; Norbert Wehn; Abdelmajid Bouajila; Johannes Zeppenfeld; Walter Stechele; Andreas Herkersdorf; Daniel Ziener; Jürgen Teich (DATE, 2010)

Using the Power Side Channel of FPGAs for Communication. - Daniel Ziener; Florian Baueregger; Jürgen Teich (FCCM, 2010)

Multiplexing Methods for Power Watermarking. - Daniel Ziener; Florian Baueregger; Jürgen Teich (HOST, 2010)

Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs. - Daniel Ziener (2010)

Symbolic design space exploration for multi-mode reconfigurable systems. - Stefan Wildermann; Felix Reimann; Daniel Ziener; Jürgen Teich (CODES+ISSS, 2011)

Stress-Aware Module Placement on Reconfigurable Devices. - Josef Angermeier; Daniel Ziener; Michael Glaß; Jürgen Teich (FPL, 2011)

Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs. - Stefan Wildermann; Jürgen Teich; Daniel Ziener (FPL, 2011)

Runtime stress-aware replica placement on reconfigurable devices under safety constraints. - Josef Angermeier; Daniel Ziener; Michael Glaß; Jürgen Teich (FPT, 2011)

An FPGA implementation of a threat-based strategy for Connect6. - Tobias Ziermann; Bernhard Schmidt; Moritz Mühlenthaler; Daniel Ziener; Josef Angermeier; Jürgen Teich (FPT, 2011)

Partial Reconfiguration on FPGAs in Practice - Tools and Applications. - Dirk Koch; Jim Tørresen; Christian Beckhoff; Daniel Ziener; Christopher Dennl; Volker Breuer; Jürgen Teich; Michael Feilen; Walter Stechele (ARCS Workshops, 2012)

On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library. - Christopher Dennl; Daniel Ziener; Jürgen Teich (FCCM, 2012)

FPGA-based testbed for timing behavior evaluation of the Controller Area Network (CAN). - Tobias Ziermann; Alexander Butiu; Jürgen Teich; Daniel Ziener (ReConFig, 2012)

Acceleration of SQL Restrictions and Aggregations through FPGA-Based Dynamic Partial Reconfiguration. - Christopher Dennl; Daniel Ziener; Jürgen Teich (FCCM, 2013)

Symbolic system-level design methodology for multi-mode reconfigurable systems. - Stefan Wildermann; Felix Reimann; Daniel Ziener; Jürgen Teich (Des. Autom. Embed. Syst., 2013)

A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor. - Robért Glein; Bernhard Schmidt; Florian Rittner; Jürgen Teich; Daniel Ziener (FCCM, 2014)

An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only). - Bernhard Schmidt; Daniel Ziener; Jürgen Teich (FPGA, 2014)

Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration. - Andreas Becher; Florian Bauer; Daniel Ziener; Jürgen Teich (FPL, 2014)

Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning. - Bernhard Schmidt; Daniel Ziener; Jürgen Teich (IPDPS Workshops, 2014)

Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014). - Frank Hannig; Dirk Koch; Daniel Ziener (CoRR, 2014)

Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy. - Robért Glein; Florian Rittner; Andreas Becher; Daniel Ziener; Jürgen Frickel; Jürgen Teich; Albert Heuberger (AHS, 2015)

A co-design approach for accelerated SQL query processing via FPGA-based data filtering. - Andreas Becher; Daniel Ziener; Klaus Meyer-Wegener; Jürgen Teich (FPT, 2015)

Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015). - Frank Hannig; Dirk Koch; Daniel Ziener (CoRR, 2015)

FPGA Versus Software Programming: Why, When, and How? - Dirk Koch; Daniel Ziener; Frank Hannig (FPGAs for Software Programmers, 2016)

A LUT-Based Approximate Adder. - Andreas Becher; Jorge Echavarria; Daniel Ziener; Stefan Wildermann; Jürgen Teich (FCCM, 2016)

FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs. - Jorge Echavarria; Stefan Wildermann; Andreas Becher; Jürgen Teich; Daniel Ziener (FPT, 2016)

Efficient deep neural network acceleration through FPGA-based batch processing. - Thorbjörn Posewsky; Daniel Ziener (ReConFig, 2016)

FPGA-Based Dynamically Reconfigurable SQL Query Processing. - Daniel Ziener; Florian Bauer; Andreas Becher; Christopher Dennl; Klaus Meyer-Wegener; Ute Schürfeld; Jürgen Teich; Jörg-Stephan Vogt; Helmut Weber (ACM Trans. Reconfigurable Technol. Syst., 2016)

Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning. - Bernhard Schmidt; Daniel Ziener; Jürgen Teich; Christian Zöllner 003 (Integr., 2017)

Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems - Daniel Michael Ziener (2017)

A Flexible FPGA-Based Inference Architecture for Pruned Deep Neural Networks. - Thorbjörn Posewsky; Daniel Ziener (ARCS, 2018)

Configuration Tampering of BRAM-based AES Implementations on FPGAs. - Daniel Ziener; Jutta Pirkl; Jürgen Teich (ReConFig, 2018)

Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems. - Daniel Ziener (CoRR, 2018)

Throughput optimizations for FPGA-based deep neural network inference. - Thorbjörn Posewsky; Daniel Ziener (Microprocess. Microsystems, 2018)

Optimizing FPGA-Based Streaming Applications for Throughput Using Pipelining. - Ali Asghar; Rick van Loo; Timon Kruiper; Daniel Ziener (FPT, 2019)

A Complete Open Source Design Flow for Gowin FPGAs. - Pepijn de Vos; Michael Kirchhoff; Daniel Ziener (FPT, 2020)

Increasing Side-Channel Resistance by Netlist Randomization and FPGA-Based Reconfiguration. - Ali Asghar; Benjamin Hettwer; Emil Karimov; Daniel Ziener (ARC, 2021)

Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration. - Hasan Irmak; Daniel Ziener; Nikolaos Alachiotis 001 (FPL, 2021)

An Energy-Efficient FPGA-based Convolutional Neural Network Implementation. - Hasan Irmak; Nikolaos Alachiotis 001; Daniel Ziener (SIU, 2021)

Using Look Up Table Content as Signatures to Identify IP Cores in Modern FPGAs. - Ali Asghar; Amanda Katherine Robillard; Ilya Tuzov; Andreas Becher; Daniel Ziener (ARCS, 2022)

Short Paper: Analysis of Vivado implementation strategies regarding side-channel leakage for FPGA-based AES implementations. - Ali Asghar; Andreas Becher; Daniel Ziener (HASP@MICRO, 2024)