A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction. - Colin Weltin-Wu; Enrico Temporiti; Daniele Baldi; Francesco Svelto (ISSCC, 2008)

Insights into wideband fractional All-Digital PLLs for RF applications. - Enrico Temporiti; Colin Weltin-Wu; Daniele Baldi; Riccardo Tonietto; Francesco Svelto (CICC, 2009)

A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication. - Massimo Pozzoni; Simone Erba; Paolo Viola; Matteo Pisati; Emanuele Depaoli; Davide Sanzogni; Riccardo Brama; Daniele Baldi; Matteo Repossi; Francesco Svelto (IEEE J. Solid State Circuits, 2009)

A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques. - Enrico Temporiti; Colin Weltin-Wu; Daniele Baldi; Riccardo Tonietto; Francesco Svelto (IEEE J. Solid State Circuits, 2009)

A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization. - Massimo Pozzoni; Simone Erba; Davide Sanzogni; Marcello Ganzerli; Paolo Viola; Daniele Baldi; Matteo Repossi; Giorgio Spelgatti; Francesco Svelto (ISSCC, 2010)

A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation. - Colin Weltin-Wu; Enrico Temporiti; Daniele Baldi; Marco Cusmai; Francesco Svelto (ISSCC, 2010)

A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation. - Enrico Temporiti; Colin Weltin-Wu; Daniele Baldi; Marco Cusmai; Francesco Svelto (IEEE J. Solid State Circuits, 2010)

Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs. - Colin Weltin-Wu; Enrico Temporiti; Marco Cusmai; Daniele Baldi; Francesco Svelto (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4. - Dan Li; Gabriele Minoia; Matteo Repossi; Daniele Baldi; Enrico Temporiti; Andrea Mazzanti; Francesco Svelto (ESSCIRC, 2012)

A 5th order gm-C low-pass filter with ±3% cut-off frequency accuracy and 220MHz to 3.3GHz tuning-range in 28nm LP CMOS. - Nicolo Sabatino; Gabriele Minoia; M. Roche; Daniele Baldi; Enrico Temporiti; Andrea Mazzanti (ESSCIRC, 2014)

A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies. - Enrico Temporiti; Gabriele Minoia; Matteo Repossi; Daniele Baldi; Andrea Ghilioni; Francesco Svelto (ESSCIRC, 2014)

A Low-Noise Design Technique for High-Speed CMOS Optical Receivers. - Dan Li; Gabriele Minoia; Matteo Repossi; Daniele Baldi; Enrico Temporiti; Andrea Mazzanti; Francesco Svelto (IEEE J. Solid State Circuits, 2014)

22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s. - Marco Cignoli; Gabriele Minoia; Matteo Repossi; Daniele Baldi; Andrea Ghilioni; Enrico Temporiti; Francesco Svelto (ISSCC, 2015)

A 25Gb/s 3D-integrated silicon photonics receiver in 65nm CMOS and PIC25G for 100GbE optical links. - Dan Li; Gabriele Minoia; Matteo Repossi; Daniele Baldi; Andrea Ghilioni; Enrico Temporiti; Francesco Svelto (ISCAS, 2016)

23.4 A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologies. - Enrico Temporiti; Gabriele Minoia; Matteo Repossi; Daniele Baldi; Andrea Ghilioni; Francesco Svelto (ISSCC, 2016)

Insights Into Silicon Photonics Mach-Zehnder-Based Optical Transmitter Architectures. - Enrico Temporiti; Andrea Ghilioni; Gabriele Minoia; Piero Orlandi; Matteo Repossi; Daniele Baldi; Francesco Svelto (IEEE J. Solid State Circuits, 2016)

12.2 A 4-Channel 200Gb/s PAM-4 BiCMOS Transceiver with Silicon Photonics Front-Ends for Gigabit Ethernet Applications. - Enrico Sentieri; Tino Copani; Andrea Paganini; Matteo Traldi; Angelo Palladino; Antonio Santipo; Lorenzo Gerosa; Matteo Repossi; Gianluca Catrini; Marta Campo; Francesco Radice; Andrea Diodato; et al. (ISSCC, 2020)