A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology. - John F. Bulzacchelli; Troy J. Beukema; Daniel W. Storaska; Ping-Hsuan Hsieh; Sergey V. Rylov; Daniel Furrer; Daniele Gardellini; Andrea Prati 002; Christian Menolfi; David Hanson; Juergen Hertle; Thomas Morf; et al. (ISSCC, 2012)

A 28Gb/s source-series terminated TX in 32nm CMOS SOI. - Christian Menolfi; Juergen Hertle; Thomas Toifl; Thomas Morf; Daniele Gardellini; Matthias Braendli; Peter Buchmann; Marcel A. Kossel (ISSCC, 2012)

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. - John F. Bulzacchelli; Christian Menolfi; Troy J. Beukema; Daniel W. Storaska; Juergen Hertle; David Hanson; Ping-Hsuan Hsieh; Sergey V. Rylov; Daniel Furrer; Daniele Gardellini; Andrea Prati 002; Thomas Morf; et al. (IEEE J. Solid State Circuits, 2012)

A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS. - Thomas Toifl; Christian Menolfi; Michael Ruegg; Robert Reutemann; Daniel Dreps; Troy J. Beukema; Andrea Prati 002; Daniele Gardellini; Marcel A. Kossel; Peter Buchmann; Matthias Braendli; Pier Andrea Francese; et al. (IEEE J. Solid State Circuits, 2012)

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Troy J. Beukema; William R. Kelly; Hui H. Xu; David Freitas; Andrea Prati 002; Daniele Gardellini; Robert Reutemann; Giovanni Cervelli; Juergen Hertle; et al. (IEEE J. Solid State Circuits, 2014)