Daniele Rossi

According to our database1, Daniele Rossi authored at least 79 papers between 2002 and 2020.

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2020
Leveraging CMOS Aging for Efficient Microelectronics Design.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

2019
Run-time Detection and Mitigation of Power-Noise Viruses.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Analysis on Retention Time and Adaptive Refresh in Embedded DRAMs with Aging Benefits.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2018
Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Collective-Aware System-on-Chips for Dependable IoT Applications.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Recycled IC detection through aging sensor.
Proceedings of the 23rd IEEE European Test Symposium, 2018

2017
Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Aging Benefits in Nanometer CMOS Designs.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Susceptible Workload Evaluation and Protection using Selective Fault Tolerance.
J. Electron. Test., 2017

Low power probabilistic online monitoring of systematic erroneous behaviour.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Low cost error monitoring for improved maintainability of IoT applications.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016
Reliable Power Gating With NBTI Aging Benefits.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST.
IEEE Trans. Computers, 2016

The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology.
Microelectron. Reliab., 2016

Analysis of BTI aging of level shifters.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

BTI aware thermal management for reliable DVFS designs.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

2015
Impact of Bias Temperature Instability on Soft Error Susceptibility.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Modeling and Detection of Hotspot in Shaded Photovoltaic Cells.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Low-Cost On-Chip Clock Jitter Measurement Scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2015

DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

BTI and leakage aware dynamic voltage scaling for reliable low power cache memories.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Diagnosis of power switches with power-distribution-network consideration.
Proceedings of the 20th IEEE European Test Symposium, 2015

NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating.
Proceedings of the 20th IEEE European Test Symposium, 2015

2014
Clock Faults Induced Min and Max Delay Violations.
J. Electron. Test., 2014

Power droop reduction during Launch-On-Shift scan-based logic BIST.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013
Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Low Cost NBTI Degradation Detection and Masking Approaches.
IEEE Trans. Computers, 2013

Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder.
J. Electron. Test., 2013

Novel approach to reduce power droop during scan-based logic BIST.
Proceedings of the 18th IEEE European Test Symposium, 2013

2012
Faults affecting the control blocks of PV arrays and techniques for their concurrent detection.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
Impact of Aging Phenomena on Soft Error Susceptibility.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Model for Thermal Behavior of Shaded Photovoltaic Cells under Hot-Spot Condition.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Error correcting code analysis for cache memory high reliability and performance.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
High-Performance Robust Latches.
IEEE Trans. Computers, 2010

Secure communication protocol for wireless sensor networks.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Transient Fault and Soft Error On-die Monitoring Scheme.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors.
Proceedings of the 7th Conference on Computing Frontiers, 2010

Novel low-cost aging sensor.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2009
Accurate Linear Model for SET Critical Charge Estimation.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Novel High Speed Robust Latch.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008
Power Consumption of Fault Tolerant Busses.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Checkers' No-Harm Alarms and Design Approaches to Tolerate Them.
J. Electron. Test., 2008

Simultaneous Switching Noise: The Relation between Bus Layout and Coding.
IEEE Des. Test Comput., 2008

Risks for Signal Integrity in System in Package and Possible Remedies.
Proceedings of the 13th European Test Symposium, 2008

Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic.
Proceedings of the 13th European Test Symposium, 2008

2007
Latch Susceptibility to Transient Faults and New Hardening Approach.
IEEE Trans. Computers, 2007

Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?.
IEEE Trans. Computers, 2007

Configurable Error Control Scheme for NoC Signal Integrity.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

2006
Checker No-Harm Alarm Robustness.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Can Clock Faults be Detected Through Functional Test?
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Analysis of the impact of bus implemented EDCs on on-chip SSN.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Low Cost and High Speed Embedded Two-Rail Code Checker.
IEEE Trans. Computers, 2005

Self-Checking Voter for High Speed TMR Systems.
J. Electron. Test., 2005

New ECC for Crosstalk Impact Minimization.
IEEE Des. Test Comput., 2005

Exploiting ECC Redundancy to Minimize Crosstalk Impact.
IEEE Des. Test Comput., 2005

Low Cost Scheme for On-Line Clock Skew Compensation.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Coding Techniques for Low Switching Noise in Fault Tolerant Busses.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

On Transistor Level Gate Sizing for Increased Robustness to Transient Faults.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Multiple Transient Faults in Logic: An Issue for Next Generation ICs.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

The Other Side of the Timing Equation: a Result of Clock Faults.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004
Model for Transient Fault Susceptibility of Combinational Circuits.
J. Electron. Test., 2004

Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

New High Speed CMOS Self-Checking Voter.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Fast and Low-Cost Clock Deskew Buffer.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

2003
Error Correcting Strategy for High Speed and High Density Reliable Flash Memories.
J. Electron. Test., 2003

Novel Transient Fault Hardened Static Latch.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Crosstalk Effect Minimization for Encoded Busses.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Power Consumption of Fault Tolerant Codes: the Active Elements.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

A Model for Transient Fault Propagation in Combinatorial Logic.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Error Correcting Codes for Crosstalk Effect Minimization.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

High Speed and Highly Testable Parallel Two-Rail Code Checker.
Proceedings of the 2003 Design, 2003

2002
Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

Coding Scheme for Low Energy Consumption Fault-Tolerant Bus.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002


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