Coding Scheme for Low Energy Consumption Fault-Tolerant Bus. - Daniele Rossi 001; Steven V. E. S. van Dijk; Richard P. Kleihorst; A. H. Nieuwland; Cecilia Metra (IOLTW, 2002)

Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories. - Daniele Rossi 001; Cecilia Metra; Bruno Riccò (MTDT, 2002)

High Speed and Highly Testable Parallel Two-Rail Code Checker. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (DATE, 2003)

Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors. - Cecilia Metra; T. M. Mak; Daniele Rossi 001 (DFT, 2003)

Error Correcting Codes for Crosstalk Effect Minimization. - Daniele Rossi 001; S. Cavallotti; Cecilia Metra (DFT, 2003)

A Model for Transient Fault Propagation in Combinatorial Logic. - Martin Omaña 001; Giacinto Papasso; Daniele Rossi 001; Cecilia Metra (IOLTS, 2003)

Power Consumption of Fault Tolerant Codes: the Active Elements. - Daniele Rossi 001; Steven V. E. S. van Dijk; Richard P. Kleihorst; André K. Nieuwland; Cecilia Metra (IOLTS, 2003)

Crosstalk Effect Minimization for Encoded Busses. - L. Di Silvio; Daniele Rossi 001; Cecilia Metra (IOLTS, 2003)

Novel Transient Fault Hardened Static Latch. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (ITC, 2003)

Error Correcting Strategy for High Speed and High Density Reliable Flash Memories. - Daniele Rossi 001; Cecilia Metra (J. Electron. Test., 2003)

Fast and Low-Cost Clock Deskew Buffer. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (DFT, 2004)

New High Speed CMOS Self-Checking Voter. - José Manuel Cazeaux; Daniele Rossi 001; Cecilia Metra (IOLTS, 2004)

Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems. - Daniele Rossi 001; A. Muccio; André K. Nieuwland; Atul Katoch; Cecilia Metra (IOLTS, 2004)

Model for Transient Fault Susceptibility of Combinational Circuits. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (J. Electron. Test., 2004)

The Other Side of the Timing Equation: a Result of Clock Faults. - Cecilia Metra; Martin Omaña 001; Daniele Rossi 001; José Manuel Cazeaux; T. M. Mak (DFT, 2005)

Multiple Transient Faults in Logic: An Issue for Next Generation ICs. - Daniele Rossi 001; Martin Omaña 001; Fabio Toma; Cecilia Metra (DFT, 2005)

On Transistor Level Gate Sizing for Increased Robustness to Transient Faults. - José Manuel Cazeaux; Daniele Rossi 001; Martin Omaña 001; Cecilia Metra; Abhijit Chatterjee (IOLTS, 2005)

Coding Techniques for Low Switching Noise in Fault Tolerant Busses. - André K. Nieuwland; Atul Katoch; Daniele Rossi 001; Cecilia Metra (IOLTS, 2005)

Low Cost Scheme for On-Line Clock Skew Compensation. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (VTS, 2005)

Exploiting ECC Redundancy to Minimize Crosstalk Impact. - Daniele Rossi 001; André K. Nieuwland; Atul Katoch; Cecilia Metra (IEEE Des. Test Comput., 2005)

New ECC for Crosstalk Impact Minimization. - Daniele Rossi 001; André K. Nieuwland; Atul Katoch; Cecilia Metra (IEEE Des. Test Comput., 2005)

Self-Checking Voter for High Speed TMR Systems. - José Manuel Cazeaux; Daniele Rossi 001; Cecilia Metra (J. Electron. Test., 2005)

Low Cost and High Speed Embedded Two-Rail Code Checker. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (IEEE Trans. Computers, 2005)

Fault tolerant systems. - Daniele Rossi 001 (2005)

Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects. - Martin Omaña 001; José Manuel Cazeaux; Daniele Rossi 001; Cecilia Metra (DATE, 2006)

Analysis of the impact of bus implemented EDCs on on-chip SSN. - Daniele Rossi 001; Carlo Steiner; Cecilia Metra (DATE, 2006)

Can Clock Faults be Detected Through Functional Test? - Cecilia Metra; Daniele Rossi 001; Martin Omaña 001; José Manuel Cazeaux; T. M. Mak (DDECS, 2006)

Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. - Cecilia Metra; Martin Omaña 001; Daniele Rossi 001; José Manuel Cazeaux; T. M. Mak (IOLTS, 2006)

Checker No-Harm Alarm Robustness. - Daniele Rossi 001; Martin Omaña 001; Cecilia Metra; Andrea Pagni (IOLTS, 2006)

Configurable Error Control Scheme for NoC Signal Integrity. - Daniele Rossi 001; Paolo Angelini; Cecilia Metra (IOLTS, 2007)

Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?. - Cecilia Metra; Daniele Rossi 001; T. M. Mak (IEEE Trans. Computers, 2007)

Latch Susceptibility to Transient Faults and New Hardening Approach. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (IEEE Trans. Computers, 2007)

Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic. - Cecilia Metra; Daniele Rossi 001; Martin Omaña 001; Abhijit Jas; Rajesh Galivanche (ETS, 2008)

Risks for Signal Integrity in System in Package and Possible Remedies. - Daniele Rossi 001; Paolo Angelini; Cecilia Metra; Giovanni Campardo; Gian Pietro Vanalli (ETS, 2008)

Simultaneous Switching Noise: The Relation between Bus Layout and Coding. - Daniele Rossi 001; André K. Nieuwland; Cecilia Metra (IEEE Des. Test Comput., 2008)

Checkers' No-Harm Alarms and Design Approaches to Tolerate Them. - Daniele Rossi 001; Martin Omaña 001; Cecilia Metra (J. Electron. Test., 2008)

Power Consumption of Fault Tolerant Busses. - Daniele Rossi 001; André K. Nieuwland; Steven V. E. S. van Dijk; Richard P. Kleihorst; Cecilia Metra (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Novel High Speed Robust Latch. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (DFT, 2009)

Accurate Linear Model for SET Critical Charge Estimation. - Daniele Rossi 001; José Manuel Cazeaux; Martin Omaña 001; Cecilia Metra; Abhijit Chatterjee (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Novel low-cost aging sensor. - Martin Omaña 001; Daniele Rossi 001; Nicolò Bosio; Cecilia Metra (Conf. Computing Frontiers, 2010)

Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. - Daniele Rossi 001; Martin Omaña 001; Gianluca Berghella; Cecilia Metra; Abhijit Jas; Chandra Tirumurti; Rajesh Galivanche (Conf. Computing Frontiers, 2010)

Transient Fault and Soft Error On-die Monitoring Scheme. - Daniele Rossi 001; Martin Omaña 001; Cecilia Metra (DFT, 2010)

Secure communication protocol for wireless sensor networks. - Daniele Rossi 001; Martin Omaña 001; Daniele Giaffreda; Cecilia Metra (EWDTS, 2010)

High-Performance Robust Latches. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (IEEE Trans. Computers, 2010)

Error correcting code analysis for cache memory high reliability and performance. - Daniele Rossi 001; N. Timoncini; M. Spica; Cecilia Metra (DATE, 2011)

Model for Thermal Behavior of Shaded Photovoltaic Cells under Hot-Spot Condition. - Daniele Giaffreda; Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (DFT, 2011)

Impact of Aging Phenomena on Soft Error Susceptibility. - Daniele Rossi 001; Martin Omaña 001; Cecilia Metra; Alessandro Paccagnella (DFT, 2011)

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies. - Cristiana Bolchini; Antonio Miele; Chiara Sandionigi; Marco Ottavi; Salvatore Pontarelli; Adelio Salsano; Cecilia Metra; Martin Omaña 001; Daniele Rossi 001; Matteo Sonza Reorda; Luca Sterpone; Massimo Violante; et al. (DFT, 2012)

Faults affecting the control blocks of PV arrays and techniques for their concurrent detection. - Martin Omaña 001; Daniele Rossi 001; G. Collepalumbo; Cecilia Metra; Fabrizio Lombardi (DFT, 2012)

Novel approach to reduce power droop during scan-based logic BIST. - Martin Omaña 001; Daniele Rossi 001; Filippo Fuzzi; Cecilia Metra; Chandra Tirumurti; R. Galivache (ETS, 2013)

Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder. - Daniele Rossi 001; Martin Omaña 001; G. Garrammone; Cecilia Metra; Abhijit Jas; Rajesh Galivanche (J. Electron. Test., 2013)

Low Cost NBTI Degradation Detection and Masking Approaches. - Martin Omaña 001; Daniele Rossi 001; Nicolò Bosio; Cecilia Metra (IEEE Trans. Computers, 2013)

Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection. - Martin Omaña 001; Daniele Rossi 001; Daniele Giaffreda; Roberto Specchia; Cecilia Metra; Marcin Marzencki; Bozena Kaminska (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Power droop reduction during Launch-On-Shift scan-based logic BIST. - Martin Omaña 001; Daniele Rossi 001; Edda Beniamino; Cecilia Metra; Chandra Tirumurti; Rajesh Galivanche (DFT, 2014)

Clock Faults Induced Min and Max Delay Violations. - Daniele Rossi 001; Martin Omaña 001; José Manuel Cazeaux; Cecilia Metra; T. M. Mak (J. Electron. Test., 2014)

NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating. - Daniele Rossi 001; Vasileios Tenentes; S. Saqib Khursheed; Bashir M. Al-Hashimi (ETS, 2015)

Diagnosis of power switches with power-distribution-network consideration. - Vasileios Tenentes; Daniele Rossi 001; S. Saqib Khursheed; Bashir M. Al-Hashimi (ETS, 2015)

BTI and leakage aware dynamic voltage scaling for reliable low power cache memories. - Daniele Rossi 001; Vasileios Tenentes; S. Saqib Khursheed; Bashir M. Al-Hashimi (IOLTS, 2015)

DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test. - Vasileios Tenentes; S. Saqib Khursheed; Daniele Rossi 001; Sheng Yang 003; Bashir M. Al-Hashimi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Low-Cost On-Chip Clock Jitter Measurement Scheme. - Martin Omaña 001; Daniele Rossi 001; Daniele Giaffreda; Cecilia Metra; T. M. Mak; Asifur Rahman; Simon Tam 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Modeling and Detection of Hotspot in Shaded Photovoltaic Cells. - Daniele Rossi 001; Martin Omaña 001; Daniele Giaffreda; Cecilia Metra (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Impact of Bias Temperature Instability on Soft Error Susceptibility. - Daniele Rossi 001; Martin Omaña 001; Cecilia Metra; Alessandro Paccagnella (IEEE Trans. Very Large Scale Integr. Syst., 2015)

BTI aware thermal management for reliable DVFS designs. - Hardeep Chahal; Vasileios Tenentes; Daniele Rossi 001; Bashir M. Al-Hashimi (DFT, 2016)

Analysis of BTI aging of level shifters. - Jiajing Cai; Basel Halak; Daniele Rossi 001 (IOLTS, 2016)

The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology. - Basel Halak; Vasileios Tenentes; Daniele Rossi 001 (Microelectron. Reliab., 2016)

Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST. - Martin Omaña 001; Daniele Rossi 001; Edda Beniamino; Cecilia Metra; Chandrasekharan Tirumurti; Rajesh Galivanche (IEEE Trans. Computers, 2016)

Reliable Power Gating With NBTI Aging Benefits. - Daniele Rossi 001; Vasileios Tenentes; Sheng Yang 003; S. Saqib Khursheed; Bashir M. Al-Hashimi (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Low cost error monitoring for improved maintainability of IoT applications. - Mauricio D. Gutierrez; Vasileios Tenentes; Tom J. Kazmierski; Daniele Rossi 001 (DFT, 2017)

Low power probabilistic online monitoring of systematic erroneous behaviour. - Mauricio D. Gutierrez; Vasileios Tenentes; Tom J. Kazmierski; Daniele Rossi 001 (ETS, 2017)

Susceptible Workload Evaluation and Protection using Selective Fault Tolerance. - Mauricio D. Gutierrez; Vasileios Tenentes; Daniele Rossi 001; Tom J. Kazmierski (J. Electron. Test., 2017)

Aging Benefits in Nanometer CMOS Designs. - Daniele Rossi 001; Vasileios Tenentes; Sheng Yang 003; Syed Saqib Khursheed; Bashir M. Al-Hashimi (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST. - Martin Omaña 001; Daniele Rossi 001; Filippo Fuzzi; Cecilia Metra; Chandra Tirumurti; Rajesh Galivanche (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure. - Vasileios Tenentes; Daniele Rossi 001; Sheng Yang 003; S. Saqib Khursheed; Bashir M. Al-Hashimi; Steve R. Gunn (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Recycled IC detection through aging sensor. - Daniele Rossi 001; Vasileios Tenentes; S. Saqib Khursheed; Sudhakar M. Reddy (ETS, 2018)

Collective-Aware System-on-Chips for Dependable IoT Applications. - Vasileios Tenentes; Daniele Rossi 001; Bashir M. Al-Hashimi (IOLTS, 2018)

Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories. - Daniele Rossi 001; Vasileios Tenentes; Sudhakar M. Reddy; Bashir M. Al-Hashimi; Andrew D. Brown (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs. - Vasileios Tenentes; Daniele Rossi 001; S. Saqib Khursheed; Bashir M. Al-Hashimi; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Analysis on Retention Time and Adaptive Refresh in Embedded DRAMs with Aging Benefits. - Abdessamad Najdi; Daniele Rossi 001; Vasileios Tenentes (IOLTS, 2019)

Run-time Detection and Mitigation of Power-Noise Viruses. - Vasileios Tenentes; Shidhartha Das; Daniele Rossi 001; Bashir M. Al-Hashimi (IOLTS, 2019)

Leveraging CMOS Aging for Efficient Microelectronics Design. - Antonio Leonel Hernández Martínez; S. Saqib Khursheed; Daniele Rossi 001 (IOLTS, 2020)

Differential Aging Sensor to Detect Recycled ICs using Sub-threshold Leakage Current. - Turki Alnuayri; S. Saqib Khursheed; Antonio Leonel Hernández Martínez; Daniele Rossi 001 (DATE, 2021)

Differential Aging Sensor Using Subthreshold Leakage Current to Detect Recycled ICs. - Turki Alnuayri; S. Saqib Khursheed; Antonio Leonel Hernández Martínez; Daniele Rossi 001 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A 2 GHz Wide Tuning Range LC-Tank Digitally Controlled Oscillator in 28 nm CMOS Technology. - Gabriele Ciarpi; G. Puccioni; Marco Mestice; Danilo Monda; Daniele Rossi 001; Sergio Saponara (ApplePies, 2022)

A Low-Area, Low-Power, Wide Tuning Range Digitally Controlled Oscillator for Power Management Systems in 28 nm CMOS Technology. - Marco Mestice; G. Biondi; Gabriele Ciarpi; Daniele Rossi 001; Sergio Saponara (ApplePies, 2022)

Novel BTI Robust Ring-Oscillator-Based Physically Unclonable Function. - Marco Grossi; Martin Omaña 001; Daniele Rossi 001; Biagio Marzulli; Cecilia Metra (IOLTS, 2022)

Online Remaining Useful Lifetime Prediction Using Support Vector Regression. - Antonio Leonel Hernández Martínez; Saqib Khursheed; Turki Alnuayri; Daniele Rossi 001 (IEEE Trans. Emerg. Top. Comput., 2022)

Hardware Trojan Detection on a PCB Through Differential Power Monitoring. - Gor Piliposyan; Saqib Khursheed; Daniele Rossi 001 (IEEE Trans. Emerg. Top. Comput., 2022)

Wire Bonding: Limitations and Opportunities for High-Speed Serial Communications. - Gabriele Ciarpi; Marco Mestice; Daniele Rossi 001; Sergio Saponara (ApplePies, 2023)

Smart Kinetic Floor System for Energy Harvesting and Data Acquisition in High Foot-Traffic Areas. - Gabriele Ciarpi; Ettore Noccetti; Luca Ceragioli; Marco Mestice; Daniele Rossi 001; Sergio Saponara (ApplePies, 2023)

10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation Environments. - Gabriele Ciarpi; Marco Mestice; Daniele Rossi 001; Fabrizio Palla; Sergio Saponara (ICECS, 2023)

Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures. - Daniele Rossi 001; Nicasio Canino; Stefano Di Matteo; Sergio Saponara; Vasileios Tenentes (SEEDA-CECNSM, 2023)

Embedded Platforms for Trusted Edge Computing Towards Quality Assurance Along the Supply Chain. - Vasileios Tenentes; Athanasios Xynos; Christos Zonios; Asimina Koutra; Christina Dilopoulou; Konstantinos Tsampiras; Yiorgos Tsiatouhas; Daniele Rossi 001 (SEEDA-CECNSM, 2023)

A 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation-Pervaded and High-Temperature Applications. - Gabriele Ciarpi; Marco Mestice; Daniele Rossi 001; Fabrizio Palla; Sergio Saponara (IEEE Access, 2023)

HARDNESS: Hardware-Supported Post Quantum Over-the-Air Software Update and Intrusion Detection System for Next Generation Secure Cars. - Cinzia Bernardeschi; Nicasio Canino; Gianluca Dini; Pierpaolo Dini; Daniele Rossi 001; Federico Rossi 003; Sergio Saponara (ApplePies, 2024)

An Area-Oriented Approach to the System-Level Design of Charge-Pump Phase-Locked Loops. - Marco Mestice; Gabriele Ciarpi; Daniele Rossi 001; Sergio Saponara (ApplePies, 2024)

Design of an Ultra-wideband Multiple-Mode Resonator (MMR)-Based High Selectivity Bandpass Filter. - Rathod Rajender; Gabriele Ciarpi; Simone Genovesi; Daniele Rossi 001 (ApplePies, 2024)

RTL Flow for the Power Side-Channel Resilience Assessment of a Post-Quantum SHA-3 Accelerator. - Vasileios Tenentes; Stefano Di Matteo; Christos Zonios; Daniele Rossi 001; Sergio Saponara (MOCAST, 2024)

HW-SW Interface Design and Implementation for Error Logging and Reporting for RAS Improvement. - Nicasio Canino; Stefano Di Matteo; Daniele Rossi 001; Sergio Saponara (IEEE Access, 2024)

Design and Experimental Verification of a 6.25-GHz PLL for Harsh Temperature Conditions in 65-nm CMOS Technology. - Marco Mestice; Gabriele Ciarpi; Daniele Rossi 001; Sergio Saponara (IEEE Trans. Instrum. Meas., 2024)

Autoencoder-Based Detection of Physical-Layer Anomalies in Automotive CAN Networks. - Antonio Battaglia; Nicasio Canino; Pierpaolo Dini; Giovanni Lombardo; Francesco Longo 001; Daniele Rossi 001 (IOLTS, 2025)

On-Chip Age Estimation Using Machine Learning. - Turki Alnuayri; Saqib Khursheed; Daniele Rossi 001 (IEEE Access, 2025)

CANini: In-Depth Traffic Analysis for Design and Robustness Evaluation of DTree-Based IDS in Automotive Networking Systems. - Nicasio Canino; Pierpaolo Dini; Stefano Mazzetti; Daniele Rossi 001; Sergio Saponara (IEEE Access, 2025)