Characterization of Locked Sequential Circuits via ATPG. - Danielle Duvalsaint; Zeye Liu 001; Ananya Ravikumar; Ronald D. Blanton (ITC-Asia, 2019)

Characterization of Locked Combinational Circuits via ATPG. - Danielle Duvalsaint; Xiaoxiao Jin; Benjamin Niewenhuis; R. D. (Shawn) Blanton (ITC, 2019)

Special Session: Novel Attacks on Logic-Locking. - Ayush Jain 002; Ujjwal Guin; M. Tanjidur Rahman; Navid Asadizanjani; Danielle Duvalsaint; R. D. Shawn Blanton (VTS, 2020)

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. - Benjamin Tan 001; Ramesh Karri; Nimisha Limaye; Abhrajit Sengupta; Ozgur Sinanoglu; Md. Moshiur Rahman 001; Swarup Bhunia; Danielle Duvalsaint; Ronald D. Blanton; Amin Rezaei 001; Yuanqi Shen; Hai Zhou 001; et al. (CoRR, 2020)

Characterizing Corruptibility of Logic Locks using ATPG. - Danielle Duvalsaint; R. D. Shawn Blanton (ITC, 2021)

Secuirty Metrics for Logic Circuits. - Ruben Purdy; Danielle Duvalsaint; R. D. Shawn Blanton (HOST, 2022)

PEPR: Pseudo-Exhaustive Physically-Aware Region Testing. - Wei Li; Chris Nigh; Danielle Duvalsaint; Subhasish Mitra; Ronald D. Blanton (ITC, 2022)

Measuring Security Metrics of Locked Circuits with Test - Danielle Duvalsaint (2023)