Fast cone-of-influence computation and estimation in problems with multiple properties. - Carmelo Loiacono; Marco Palena; Paolo Pasini; Denis Patti; Stefano Quer; Stefano Ricossa; Danilo Vendraminetto; Jason Baumgartner (DATE, 2013)

Tightening BDD-based approximate reachability with SAT-based clause generalization∗. - Gianpiero Cabodi; Paolo Pasini; Stefano Quer; Danilo Vendraminetto (DATE, 2014)

Hardware Model Checking Competition 2014: An Analysis and Comparison of Solvers and Benchmarks. - Gianpiero Cabodi; Carmelo Loiacono; Marco Palena; Paolo Pasini; Denis Patti; Stefano Quer; Danilo Vendraminetto; Armin Biere; Keijo Heljanko (J. Satisf. Boolean Model. Comput., 2014)

Optimization techniques for craig interpolant compaction in unbounded model checking. - Gianpiero Cabodi; Carmelo Loiacono; Danilo Vendraminetto (Formal Methods Syst. Des., 2015)

Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening. - Gianpiero Cabodi; Paolo Camurati; Marco Palena; Paolo Pasini; Danilo Vendraminetto (FMCAD, 2016)

Secure Path Verification. - Gianpiero Cabodi; Paolo Camurati; Sebastiano F. Finocchiaro; Carmelo Loiacono; Francesco Savarese; Danilo Vendraminetto (IVSW, 2016)

Advanced Techniques for Bit-Level Model Checking. - Danilo Vendraminetto (2016)

Interpolation-Based Learning as a Mean to Speed-Up Bounded Model Checking (Short Paper). - Gianpiero Cabodi; Paolo Camurati; Marco Palena; Paolo Pasini; Danilo Vendraminetto (SEFM, 2017)

Embedded Systems Secure Path Verification at the Hardware/Software Interface. - Gianpiero Cabodi; Paolo Camurati; Sebastiano F. Finocchiaro; Francesco Savarese; Danilo Vendraminetto (IEEE Des. Test, 2017)

Model Checking Speculation-Dependent Security Properties: Abstracting and Reducing Processor Models for Sound and Complete Verification. - Gianpiero Cabodi; Paolo Camurati; Fabrizio F. Finocchiaro; Danilo Vendraminetto (C2SI, 2019)

Logic Synthesis for Interpolant Circuit Compaction. - Gianpiero Cabodi; Paolo Camurati; Marco Palena; Paolo Pasini; Danilo Vendraminetto (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Reducing Interpolant Circuit Size Through SAT-Based Weakening. - Gianpiero Cabodi; Paolo Camurati; Marco Palena; Paolo Pasini; Danilo Vendraminetto (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)