HAHMF: Heuristic-Augmented Asymmetric Heterogeneous Splitting for Hardware Efficient Multipliers Framework. - Saketh Gajawada; Dantu Nandini Devi; Madhav Rao (DSD, 2024)

Integrated MAC-based Systolic Arrays: Design and Performance Evaluation. - Dantu Nandini Devi; Gandi Ajay Kumar; Bindu G. Gowda; Madhav Rao (ACM Great Lakes Symposium on VLSI, 2024)

Performance-Aware Design of Approximate Integrated MAC Factored Systolic Array Accelerators. - Dantu Nandini Devi; Gandi Ajay Kumar; Bindu G. Gowda; Madhav Rao (ISQED, 2024)

PSO Optimized Design of Error Balanced Weight Stationary Systolic Array Architecture for CNN. - Dantu Nandini Devi; Gandi Ajay Kumar; Bindu G. Gowda; Madhav Rao (ISQED, 2024)

MOHSKM: Meta-Heuristic Optimization Driven Hardware-Efficient Heterogeneous-Split Karatsuba Multipliers for Large-Bit Operations. - Saketh Gajawada; Dantu Nandini Devi; Madhav Rao (ISVLSI, 2024)

OEDASA: Optimization Enabled Error-Diluted Approximate Systolic Array Design for an Image Processing Application. - Dantu Nandini Devi; Gandi Ajay Kumar; Bindu G. Gowda; Madhav Rao (VLSID, 2024)

Precision-Factored Systolic Arrays: Balancing Accuracy and Efficiency in Floating-Point Computations for CNNs. - Dantu Nandini Devi; Madhav Rao (ISCAS, 2025)

LibApprox: A Comprehensive Library for Performance Efficient Approximate Circuits. - D. V. Bhargav; Dantu Nandini Devi; Rachana Kaparthi; Madhav Rao (ISQED, 2025)

Design of Hardware-Efficient Inexact Multiplier Using Evolutionary Algorithm Factored by Multi-Variate Approximation. - Dantu Nandini Devi; Saketh Gajawada; Madhav Rao (ISQED, 2025)

Meta-Heuristic Optimization for Designing Error Diluted Weight Stationary Approximate Systolic Array Architecture. - Dantu Nandini Devi; Bindu G. Gowda; Madhav Rao (ISQED, 2025)