A 45 nm 10T Dual-Port SRAM with Shared Bit-Line Scheme for Low Power Operation. - Dao-Ping Wang; Wei Hwang (J. Low Power Electron., 2012)

A Two-Write and Two-Read Multi-Port SRAM with Shared Write Bit-Line Scheme and Selective Read Path for Low Power Operation. - Dao-Ping Wang; Hon-Jarn Lin; Wei Hwang (J. Low Power Electron., 2013)

Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors. - Dao-Ping Wang; Hon-Jarn Lin; Ching-Te Chuang; Wei Hwang (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Coordination model of inventory system for deteriorating items with time-varying demand based on revenue-sharing contract. - Dao-Ping Wang; Lu Wang; Bo-qing Zhang (ICIA, 2015)

Research on the Coordination of a Dual-channel Supply Chain Considering Fairness Concern. - Dao-Ping Wang; Qing-Yu Shang; Bo-qing Zhang (ICMSS, 2017)