An Improved Global Stereo-Matching on FPGA for Real-Time Applications (Abstract Only). - Daolu Zha; Xi Jin 002; Tian Xiang (FPGA, 2016)

A real-time global stereo-matching on FPGA. - Daolu Zha; Xi Jin 002; Tian Xiang (Microprocess. Microsystems, 2016)

A Real-Time Learning-Based Super-Resolution System Using Direct Simple Functions. - Daolu Zha; Xi Jin 002; Rui Shang; Pengfei Yang (ASAP, 2018)

A pipelined division for fixed operation using user-defined floating point. - Pengfei Yang; Daolu Zha; Xi Jin 002 (ICACT, 2018)

Enhancing energy efficiency of RISC-V processor-based embedded graphics systems through frame buffer compression. - Yuzhi Zhou; Xi Jin 002; Tian Xiang; Daolu Zha (Microprocess. Microsystems, 2020)

A Real-Time Learning-Based Super-Resolution System on FPGA. - Daolu Zha; Xi Jin 002; Rui Shang; Pengfei Yang (Parallel Process. Lett., 2020)