Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory. - Sheyang Ning; Tomoko Ogura Iwasaki; Shuhei Tanakamaru; Darlene Viviani; Henry Huang; Monte Manning; Thomas Rueckes; Ken Takeuchi (IEEE J. Solid State Circuits, 2016)

NRAM status and prospects. - David C. Gilmer; Thomas Rueckes; Lee Cleveland; Darlene Viviani (ICICDT, 2017)