Shared fuse macro for multiple embedded memory devices with redundancy. - Michael R. Ouellette; Darren Anand; Peter Jakobsen (CICC, 2001)

Embedded DRAM built in self test and methodology for test insertion. - Peter Jakobsen; Jeffrey H. Dreibelbis; Gary Pomichter; Darren Anand; John Barth 001; Michael R. Nelms; Jeffrey Leach; George M. Belansek (ITC, 2001)

Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering. - John E. Barth Jr.; Jeffrey H. Dreibelbis; Eric A. Nelson; Darren Anand; Gary Pomichter; Peter Jakobsen; Michael R. Nelms; Jeffrey Leach; George M. Belansek (IBM J. Res. Dev., 2002)

An On-Chip Self-Repair Calculation and Fusing Methodology. - Darren Anand; Bruce Cowan; Owen Farnsworth; Peter Jakobsen; Steven F. Oakland; Michael Ouellette; Donald L. Wheater (IEEE Des. Test Comput., 2003)

A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. - Harold Pilo; Darren Anand; John Barth 001; Steve Burns 001; Phil Corson; Jim Covino; Steve Lamphier (IEEE J. Solid State Circuits, 2003)

Generating At-Speed Array Fail Maps with Low-Speed ATE. - Michael R. Nelms; Kevin W. Gorman; Darren Anand (VTS, 2004)

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining. - John E. Barth Jr.; Darren Anand; Steve Burns 001; Jeffrey H. Dreibelbis; John A. Fifield; Kevin W. Gorman; Michael R. Nelms; Erik Nelson; Adrian Paparelli; Gary Pomichter; Dale E. Pontius; Stephen Sliva (IEEE J. Solid State Circuits, 2005)

Low Cost Test of High Bandwidth Embedded Memories. - Kevin W. Gorman; Darren Anand; Gary Pomichter; William R. Corbin (CICC, 2006)

A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST. - Darren Anand; Jim Covino; Jeffrey H. Dreibelbis; John A. Fifield; Kevin W. Gorman; Mark Jacunski; Jake Paparelli; Gary Pomichter; Dale E. Pontius; Michael Roberge; Stephen Sliva (CICC, 2007)

A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns. - Mark Jacunski; Darren Anand; Robert Busch; John A. Fifield; Matthew Lanahan; Paul Lane; Adrian Paparelli; Gary Pomichter; Dale E. Pontius; Michael Roberge; Stephen Sliva (CICC, 2010)

Embedded DRAM in 45-nm Technology and Beyond. - Darren Anand; Kevin W. Gorman; Mark Jacunski; Adrian Paparelli (IEEE Des. Test Comput., 2011)

14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive Programming. - Eric Hunt-Schroeder; Darren Anand; John A. Fifield; Mark Jacunski; Michael Roberge; Dale E. Pontius; Kevin Batson; Toshiaki Kirihata (VLSI Circuits, 2018)

Behavioral Modeling of a Charge Trap Transistor One Time Programmable Memory. - Eric Hunt-Schroeder; Darren Anand; Edward Hwang; Aaron Cummings; Matthew Deming; Michael Roberge; Michael Ziegerhofer (NATW, 2019)