Compact Modeling of Variation in FinFET SRAM Cells. - Darsen D. Lu; Chung-Hsun Lin; Ali M. Niknejad; Chenming Hu (IEEE Des. Test Comput., 2010)

Tri-Gate Ferroelectric FET Characterization and Modelling for Online Training of Neural Networks at Room Temperature and 233K. - Sourav De 002; Md. Aftab Baig; Bo-Han Qiu; Darsen D. Lu; Po-Jung Sung; Fu. K. Hsueh; Yao-Jen Lee; Chun-Jung Su (DRC, 2020)

Compact Device Models for FinFET and Beyond. - Darsen D. Lu; Mohan V. Dunga; Ali M. Niknejad; Chenming Hu; Fu-Xiang Liang; Wei-Chen Hung; Jia-Wei Lee; Chun-Hsiang Hsu; Meng-Hsueh Chiang (CoRR, 2020)

Ferroelectric FET Compact Model for Neuromorphic. - Darsen D. Lu; Sourav De 002; Bo-Han Qiu (IEEE DataPort, 2020)

Alleviation of Temperature Variation Induced Accuracy Degradation in Ferroelectric FinFET Based Neural Network. - Sourav De 002; Yao-Jen Lee; Darsen D. Lu (CoRR, 2021)

Neuromorphic Computing with Deeply Scaled Ferroelectric FinFET in Presence of Process Variation, Device Aging and Flicker Noise. - Sourav De 002; Bo-Han Qiu; Wei-Xuan Bu; Md. Aftab Baig; Chung-Jun Su; Yao-Jen Lee; Darsen D. Lu (CoRR, 2021)

First Demonstration of Vertical Stacked Hetero-Oriented n-Ge (111)/p-Ge (100) CFET toward Mobility Balance Engineering. - X.-R. Yu; Wen Hsin Chang; T.-C. Hong; P.-J. Sung; A. Agarwal; G.-L. Luo; C.-T. Wu; K.-H. Kao; C.-J. Su; Shu-Wei Chang; W.-H. Lu; P.-Y. Fu; et al. (VLSI Technology and Circuits, 2022)

MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization. - W.-C. Lin; H.-P. Huang; Kuo-Hsing Kao; Meng-Hsueh Chiang; Darsen D. Lu; Wei-Chou Hsu; Yeong-Her Wang; William Cheng-Yu Ma; Hann-Huei Tsai; Y.-J. Lee; H.-L. Chiang; J.-F. Wang; et al. (ESSDERC, 2023)

CIMulator: A Comprehensive Simulation Platform for Computing-In-Memory Circuit Macros with Low Bit-Width and Real Memory Materials. - Hoang-Hiep Le; Md. Aftab Baig; Wei-Chen Hong; Cheng-Hsien Tsai; Cheng-Jui Yeh; Fu-Xiang Liang; I-Ting Huang; Wei-Tzu Tsai; Ting-Yin Cheng; Sourav De 002; Nan-Yow Chen; Wen-Jay Lee; et al. (CoRR, 2023)

Numerical Simulations of Gate-Granularity- Induced Subthreshold Characteristics Deterioration of MOSFETs Magnified at Cryogenic Temperatures. - Kuo-Hsing Kao; Zong-Hong Wang; Yu-Chia Pai; Chen-Chi Cheng; Darsen D. Lu; Wen-Jay Lee; Nan-Yow Chen (IEEE Access, 2024)

A Hardware Friendly Variation-Tolerant Framework for RRAM-Based Neuromorphic Computing. - Fang-Yi Gu; Cheng-Han Yang; Ing-Chao Lin; Da-Wei Chang; Darsen D. Lu; Ulf Schlichtmann (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Quantum-Chiplet: A VLSI-Like Methodology for Hierarchical Quantum Design and Verification. - Hao-Yu Lu; Yu-Ting Kao; Yeong-Jar Chang; Jason Gemsun Young; Darsen D. Lu (ISVLSI, 2025)