A uniform semantics for verilog and VHDL suitable for both simulation and verification - Daryl Stewart (2002)

Formal for everyone - Challenges in achievable multicore design and verification. - Daryl Stewart (FMCAD, 2012)

Preface of the special issue on the Conference on Formal Methods in Computer-Aided Design 2017. - Daryl Stewart; Georg Weissenbacher (Formal Methods Syst. Des., 2021)