David A. Wood

According to our database1, David A. Wood authored at least 114 papers between 1984 and 2017.

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Awards

ACM Fellow

ACM Fellow 2005, "For contributions to shared-memory multiprocessing.".

Timeline

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Bibliography

2017
Pareto Governors for Energy-Optimal Computing.
TACO, 2017

Could Compression Be of General Use? Evaluating Memory Compression across Domains.
TACO, 2017

Energy-Proportional Computing: A New Definition.
IEEE Computer, 2017

Gravel: fine-grain GPU-initiated network messages.
Proceedings of the International Conference for High Performance Computing, 2017

LogCA: A High-Level Performance Model for Hardware Accelerators.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Crossing Guard: Mediating Host-Accelerator Coherence Interactions.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016
Optimization Models for Three On-Chip Network Problems.
TACO, 2016

Yet Another Compressed Cache: A Low-Cost Yet Effective Compressed Cache.
TACO, 2016

GPGPU Footprint Models to Estimate per-Core Power.
Computer Architecture Letters, 2016

Lazy release consistency for GPUs.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

2015
A Primer on Compression in the Memory Hierarchy
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2015

Implications of Emerging 3D GPU Architecture on the Scan Primitive.
SIGMOD Record, 2015

LogCA: A Performance Model for Hardware Accelerators.
Computer Architecture Letters, 2015

gem5-gpu: A Heterogeneous CPU-GPU Simulator.
Computer Architecture Letters, 2015

Border control: sandboxing accelerators.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

GPU Computing Pipeline Inefficiencies and Optimization Opportunities in Heterogeneous CPU-GPU Processors.
Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015

Toward GPUs being mainstream in analytic processing: An initial argument using simple scan-aggregate queries.
Proceedings of the 11th International Workshop on Data Management on New Hardware, 2015

Synchronization Using Remote-Scope Promotion.
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014
Decoupled Compressed Cache: Exploiting Spatial Locality for Energy Optimization.
IEEE Micro, 2014

Skewed Compressed Caches.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Fine-grain task aggregation and coordination on GPUs.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

A comparative analysis of microarchitecture effects on CPU and GPU memory system behavior.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

Supporting x86-64 address translation for 100s of GPU lanes.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

QuickRelease: A throughput-oriented approach to release consistency on GPUs.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Resolved: specialized architectures, languages, and system software should supplant general-purpose alternatives within a decade.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014

Heterogeneous-race-free memory models.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014

2013
Optimization and Mathematical Modeling in Computer Architecture
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 9781627052108, 2013

Reuse-based online models for caches.
Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2013

Decoupled compressed cache: exploiting spatial locality for energy-optimized compressed caching.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

Heterogeneous system coherence for integrated CPU-GPU systems.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

2012
Something old and something new: P-states can borrow microarchitecture techniques too.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

UniFI: leveraging non-volatile memories for a unified fault tolerance and idle power management technique.
Proceedings of the International Conference on Supercomputing, 2012

2011
A Primer on Memory Consistency and Cache Coherence
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2011

The gem5 simulator.
SIGARCH Computer Architecture News, 2011

Calvin: Deterministic or not? Free will to choose.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Safe and efficient supervised memory systems.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

2010
WiDGET: Wisconsin decoupled grid execution tiles.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Forwardflow: a scalable core for power-constrained CMPs.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

2009
StealthTest: Low Overhead Online Software Testing Using Transactional Memory.
Proceedings of the PACT 2009, 2009

2008
TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

2007
Performance pathologies in hardware transactional memory.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

LogTM-SE: Decoupling Hardware Transactional Memory from Caches.
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

Interactions Between Compression and Prefetching in Chip Multiprocessors.
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

A Case for Deconstructing Hardware Transactional Memory Systems.
Proceedings of the Programming Models for Ubiquitous Parallelism, 02.09. - 07.09.2007, 2007

2006
IPC Considered Harmful for Multiprocessor Workloads.
IEEE Micro, 2006

ASR: Adaptive Selective Replication for CMP Caches.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

LogTM: log-based transactional memory.
Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

Supporting nested transactional memory in logTM.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

Keynote talk challenges in chip multiprocessor memory systems.
Proceedings of the 2006 workshop on Memory System Performance and Correctness, 2006

2005
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset.
SIGARCH Computer Architecture News, 2005

Evaluating scheduling policies for fine-grain communication protocols on a cluster of SMPs.
J. Parallel Distrib. Comput., 2005

Exploring Processor Design Options for Java-Based Middleware.
Proceedings of the 34th International Conference on Parallel Processing (ICPP 2005), 2005

Improving Multiple-CMP Systems Using Token Coherence.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

2004
Managing Wire Delay in Large Chip-Multiprocessor Caches.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

Adaptive Cache Compression for High-Performance Processors.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

Using Speculation to Simplify Multiprocessor Design.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

2003
Token Coherence: A New Framework for Shared-Memory Multiprocessors.
IEEE Micro, 2003

Addressing Workload Variability in Architectural Simulations.
IEEE Micro, 2003

Simulating a $2M Commercial Server on a $2K PC.
IEEE Computer, 2003

TLC: Transmission Line Caches.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

Token Coherence: Decoupling Performance and Correctness.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

Memory System Behavior of Java-Based Middleware.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

Variability in Architectural Simulations of Multi-Threaded Workloads.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

Dynamic Verification of End-to-End Multiprocessor Invariants.
Proceedings of the 2003 International Conference on Dependable Systems and Networks (DSN 2003), 2003

2002
Adaptive competitive self-organizing associative memory.
IEEE Trans. Systems, Man, and Cybernetics, Part A, 2002

Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol.
IEEE Trans. Parallel Distrib. Syst., 2002

Full-system timing-first simulation.
Proceedings of the International Conference on Measurements and Modeling of Computer Systems, 2002

SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery.
Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002

Bandwidth Adaptive Snooping.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

2000
Wisconsin Wind Tunnel II: a fast, portable parallel architecture simulator.
IEEE Concurrency, 2000

Timestamp snooping: an approach for extending SMPs.
Proceedings of the ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, 2000

1999
DBMSs on a Modern Processor: Where Does Time Go?
Proceedings of the VLDB'99, 1999

Multicast Snooping: A New Coherence Method Using a Multicast Address Network.
Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999

Parallel Dispatch Queue: A Queue-Based Programming Abstraction to Parallelize Fine-Grain Communication Protocols.
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

1998
Hardware Support for Flexible Distributed Shared Memory.
IEEE Trans. Computers, 1998

Analytic Evaluation of Shared-memory Systems with ILP Processors.
Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

Tempest and Typhoon: User-Level Shared Memory.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Retrospective: Tempest and Typhoon: User-Level Shared Memory.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Sirocco: Cost-Effective Fine-Grain Distributed Shared Memory.
Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998

1997
Modeling Cost/Performance of a Parallel Computer Simulator.
ACM Trans. Model. Comput. Simul., 1997

Relaxed Consistency and Coherence Granularity in DSM Systems: A Performance Evaluation.
Proceedings of the Sixth ACM SIGPLAN Symposium on Principles & Practice of Parallel Programming (PPOPP), 1997

Reactive NUMA: A Design for Unifying S-COMA and CC-NUMA.
Proceedings of the 24th International Symposium on Computer Architecture, 1997

Scheduling Communication on a SMP Node Parallel Machine.
Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), 1997

1996
Problems, Challenges and the Importance of Performance Evaluation.
ACM Comput. Surv., 1996

Decoupled Hardware Support for Distributed Shared Memory.
Proceedings of the 23rd Annual International Symposium on Computer Architecture, 1996

Coherent Network Interfaces for Fine-Grain Communication.
Proceedings of the 23rd Annual International Symposium on Computer Architecture, 1996

Synchronization Hardware for Networks of Workstations: Performance vs. Cost.
Proceedings of the 10th international conference on Supercomputing, 1996

The Tempest approach to distributed shared memory.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

1995
Cost-Effective Parallel Computing.
IEEE Computer, 1995

Where Is Software Headed? A Virtual Roundtable.
IEEE Computer, 1995

Active Memory: A New Abstraction for Memory-System Simulation.
Proceedings of the 1995 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems, 1995

Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors.
Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

Accuracy vs. performance in parallel simulation of interconnection networks.
Proceedings of IPPS '95, 1995

Tempest: A Substrate for Portable Parallel Programs.
Proceedings of the COMPCON '95: Technologies for the Information Superhighway, 1995

1994
A Comparison of Trace-Sampling Techniques for Multi-Megabyte Caches.
IEEE Trans. Computers, 1994

The Wisconsin Wind Tunnel project: an annotated bibliography.
SIGARCH Computer Architecture News, 1994

Cache Profiling and the SPEC Benchmarks: A Case Study.
IEEE Computer, 1994

Application-specific protocols for user-level shared memory.
Proceedings of the Proceedings Supercomputing '94, 1994

Paging tradeoffs in distributed-shared-memory multiprocessors.
Proceedings of the Proceedings Supercomputing '94, 1994

Tempest and Typhoon: User-Level Shared Memory.
Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

Fine-grain Access Control for Distributed Shared Memory.
Proceedings of the ASPLOS-VI Proceedings, 1994

1993
Wisconsin Architectural Research Tool Set.
SIGARCH Computer Architecture News, 1993

The Wisconsin Wind Tunnel: Virtual Prototyping of Parallel Computers.
Proceedings of the 1993 ACM SIGMETRICS conference on Measurement and modeling of computer systems, 1993

Kernel Support for the Wisconsin Wind Tunnel.
Proceedings of the USENIX Microkernels and Other Kernel Architectures Symposium, 1993

Mechanisms for Cooperative Shared Memory.
Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993

1992
Cooperative Shared Memory: Software and Hardware Support for Scalable Multiprocesors.
Proceedings of the ASPLOS-V Proceedings, 1992

1991
A Model for Estimating Trace-Sample Miss Ratios.
Proceedings of the 1991 ACM SIGMETRICS conference on Measurement and modeling of computer systems, 1991

Implementing Stack Simulation for Highly-Associative Memories.
Proceedings of the 1991 ACM SIGMETRICS conference on Measurement and modeling of computer systems, 1991

1990
Verifying a Multiprocessor Cache Controller Using Random Test Generation.
IEEE Design & Test of Computers, 1990

1989
Supporting Reference and Dirty Bits in SPUR's Virtual Address Cache.
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989

1986
An In-Cache Address Translation Mechanism.
Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986

1985
Implementing A Cache Consistency Protocol.
Proceedings of the 12th Annual Symposium on Computer Architecture, 1985

1984
Implementation Techniques for Main Memory Database Systems.
Proceedings of the SIGMOD'84, 1984


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