An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 μm CMOS. - Jeff L. Sonntag; John T. Stonick; James Gorecki; Bill Beale; Bill Check; Xue-Mei Gong; Joe Guiliano; Kyong Lee; Bob Lefferts; David A. Yokoyama-Martin; Un-Ku Moon; Amber Sengir; et al. (CICC, 2002)

A multigigabit backplane transceiver core in 0.13-μm CMOS with a power-efficient equalization architecture. - Kannan Krishna; David A. Yokoyama-Martin; Aaron Caffee; Chris Jones; Mat Loikkanen; James Parker; Ross Segelken; Jeff L. Sonntag; John T. Stonick; Steve Titus; Daniel Weinlader; Skye Wolfer (IEEE J. Solid State Circuits, 2005)

A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS. - David A. Yokoyama-Martin; Kannan Krishna; John T. Stonick; Aaron Caffee; E. K. Gamble; Chris Jones; J. Mcneal; James Parker; Ross Segelken; Jeff L. Sonntag; K. Umino; J. Upton; et al. (CICC, 2006)

A 224Gb/s 3pJ/bit 42dB Insertion Loss Post-FEC Error Free Transceiver in 3-nm FinFET CMOS (Invited). - Dirk Pfaff; Muhammad Nummer; Noman Hai; Jingjing Xia 001; Kai Ge Yang; Mohammad-Mahdi Mohsenpour; Choon-Haw CH Leong; Marc-Andre LaCroix; Babak Zamanlooy; Tom Eeckelaert; Dmitry Petrov; Mostafa Haroun; et al. (CICC, 2025)

A 224 Gb/s 3 pJ/bit 40 dB Insertion Loss Transceiver in 3-nm FinFET CMOS. - Dirk Pfaff; Muhammad Nummer; Noman Hai; Jingjing Xia 001; Kai Ge Yang; Mohammad-Mahdi Mohsenpour; Choon-Haw C. H. Leong; Marc-Andre LaCroix; Babak Zamanlooy; Tom Eeckelaert; Dmitry Petrov; Mostafa Haroun; et al. (IEEE J. Solid State Circuits, 2025)