PAWS: A Performance Evaluation Tool for Parallel Computing Systems. - Daniel Pease; Arif Ghafoor; Ishfaq Ahmad 001; David L. Andrews 001; Kamal Foudil-Bey; Thomas E. Karpinski; Mohammad A. Mikki; Mohamed Zerrouki (Computer, 1991)

Rapid prototype of an SIMD processor array (using FPGA's). - David L. Andrews 001; Andrew Wheeler; Barry Wealand; Cliff Kancler (RSP, 1994)

Rapid prototype of a hardware emulator for a SIMD processor array. - David L. Andrews 001; Andrew Wheeler; Barry Wealand; Cliff Kancler (ED&TC, 1995)

Graph Analysis and Transformation Techniques for Runtime Minimization in Multi-Threaded Architectures. - Mitchell A. Thornton; David L. Andrews 001 (HICSS (1), 1997)

Seeking Solutions in Configurable Computing. - William H. Mangione-Smith; Brad Hutchins; David L. Andrews 001; André DeHon; Carl Ebeling; Reiner W. Hartenstein; Oskar Mencer; John Morris; Krishna V. Palem; Viktor K. Prasanna; Henk A. E. Spaanenburg (Computer, 1997)

Integration of CAD tools and structured design principles in an undergraduate computer engineering curriculum. - David L. Andrews 001; Mitchell A. Thornton (WCAE@ISCA, 1998)

A Framework for Using Benefit Functions In Complex Real Time Systems. - David Andrews 001; Lonnie R. Welch; David M. Chelberg; Scott A. Brandt (IPDPS, 2002)

Interprocess communications in the AN/BSY-2 distributed computer system: a case study. - David Andrews 001; Paul Austin; Peter Costello; David O. LeVan (J. Syst. Softw., 2002)

A Framework for using benefit functions in complex real-time systems. - David L. Andrews 001; Ravi Vemuri; David M. Chelberg; David Fleeman; David Parrott; Lonnie R. Welch; Scott A. Brandt (Parallel Distributed Comput. Pract., 2002)

SCIMPS: An Integrated Approach to Distributed Processing in Sensor Webs. - David Andrews 001; Joe Evans; Venumadhav Mangipudi; Aditya Mandapaka (IPDPS, 2003)

Architectural Frameworks for MPP Systems on a Chip. - David Andrews 001; Douglas Niehaus (IPDPS, 2003)

Using the Multi-Threaded Computation Model as a Unifying Framework for Hardware-Software Co-Design and Implementation. - Douglas Niehaus; David Andrews 001 (WORDS Fall, 2003)

Programming Models for Hybrid CPU/FPGA Chips. - David Andrews 001; Douglas Niehaus; Peter J. Ashenden (Computer, 2004)

Programming Models for Hybrid FPGA-CPU Computational Components: A Missing Link. - David Andrews 001; Douglas Niehaus; Razali Jidin; Michael Finley; Wesley Peck; Michael Frisbie; Jorge L. Ortiz; Ed Komp; Peter J. Ashenden (IEEE Micro, 2004)

Evaluation of the Hybrid Multithreading Programming Model using Image Processing Transforms. - Razali Jidin; David Andrews 001; Wesley Peck; Dan Chirpich; Kevin Stout; John M. Gauch (IPDPS, 2005)

The Case for High Level Programming Models for Reconfigurable Computers. - David L. Andrews 001; Ron Sass; Erik K. Anderson; Jason Agron; Wesley Peck; Jim Stevens; Fabrice Baijot; Ed Komp (ERSA, 2006)

Enabling a Uniform Programming Model Across the Software/Hardware Boundary. - Erik K. Anderson; Jason Agron; Wesley Peck; Jim Stevens; Fabrice Baijot; Ed Komp; Ron Sass; David Andrews 001 (FCCM, 2006)

Hthreads: A Computational Model for Reconfigurable Devices. - Wesley Peck; Erik K. Anderson; Jason Agron; Jim Stevens; Fabrice Baijot; David Andrews 001 (FPL, 2006)

Run-Time Services for Hybrid CPU/FPGA Systems on Chip. - Jason Agron; Wesley Peck; Erik K. Anderson; David Andrews 001; Ed Komp; Ron Sass; Fabrice Baijot; Jim Stevens (RTSS, 2006)

Memory Hierarchy for MCSoPC Multithreaded Systems. - Erik K. Anderson; Wesley Peck; Jim Stevens; Jason Agron; Fabrice Baijot; Seth Warn; David L. Andrews 001 (ERSA, 2007)

Supporting High Level Language Semantics Within Hardware Resident Threads. - Erik K. Anderson; Wesley Peck; Jim Stevens; Jason Agron; Fabrice Baijot; Seth Warn; David Andrews 001 (FPL, 2007)

Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs. - Shane Santner; Wesley Peck; Jason Agron; David Andrews 001 (ARC, 2008)

An Infrastructure for Hardware-Software Co-Design of Embedded Real-Time Java Applications. - Elias Teodoro Silva Jr.; David Andrews 001; Carlos Eduardo Pereira; Flávio Rech Wagner (ISORC, 2008)

Achieving Programming Model Abstractions for Reconfigurable Computing. - David Andrews 001; Ron Sass; Erik K. Anderson; Jason Agron; Wesley Peck; Jim Stevens; Fabrice Baijot; Ed Komp (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Building heterogeneous reconfigurable systems with a hardware microkernel. - Jason Agron; David Andrews 001 (CODES+ISSS, 2009)

Building heterogeneous reconfigurable systems using threads. - Jason Agron; David Andrews 001 (FPL, 2009)

Hardware Microkernels for Heterogeneous Manycore Systems. - Jason Agron; David Andrews 001 (ICPP Workshops, 2009)

Configurable Processor Architectures: History and Trends. - David Andrews 001; Christian Plessl (ERSA, 2010)

Distributed Hardware-Based Microkernels: Making Heterogeneous OS Functionality a System Primitive. - Jason Agron; David Andrews 001 (FCCM, 2010)

Modular design of fully pipelined accumulators. - Miaoqing Huang; David Andrews 001 (FPT, 2010)

A configurable high-throughput linear sorter system. - Jorge L. Ortiz; David Andrews 001 (IPDPS Workshops, 2010)

Operating System Structures for Multiprocessor Systems on Programmable Chip. - Miaoqing Huang; David Andrews 001; Jason Agron (ReConFig, 2010)

Creating HW/SW co-designed MPSoPC's from high level programming models. - Eugene Cartwright; Sen Ma; David Andrews 001; Miaoqing Huang (HPCS, 2011)

A Streaming High-Throughput Linear Sorter System with Contention Buffering. - Jorge L. Ortiz; David Andrews 001 (Int. J. Reconfigurable Comput., 2011)

Scalable Memory Hierarchies for Embedded Manycore Systems. - Sen Ma; Miaoqing Huang; Eugene Cartwright; David Andrews 001 (ARC, 2012)

Automating the design of mLUT MPSoPC FPGAs in the cloud. - Eugene Cartwright; Azad Fahkari; Sen Ma; Christina Smith; Miaoqing Huang; David Andrews 001; Jason Agron (FPL, 2012)

Developing application-specific multiprocessor platforms on FPGAs. - Sen Ma; Miaoqing Huang; David Andrews 001 (ReConFig, 2012)

Modular Design of Fully Pipelined Reduction Circuits on FPGAs. - Miaoqing Huang; David Andrews 001 (IEEE Trans. Parallel Distributed Syst., 2013)

On energy efficiency and amdahl's law in FPGA based chip heterogeneous multiprocessor systems (abstract only). - Sen Ma; David Andrews 001 (FPGA, 2014)

Achieving portability and efficiency over chip heterogeneous multiprocessor systems. - Eugene Cartwright; Alborz Sadeghian; Sen Ma; David Andrews 001 (FPL, 2014)

Operating Systems Research for Reconfigurable Computing. - David Andrews 001 (IEEE Micro, 2014)

A Flexible Multilayer Perceptron Co-processor for FPGAs. - Zeyad Aklah; David Andrews 001 (ARC, 2015)

Automatic support for multi-module parallelism from computational patterns. - Nithin George; HyoukJoong Lee; David Novo; Muhsen Owaida; David Andrews 001; Kunle Olukotun; Paolo Ienne (FPL, 2015)

A run time interpretation approach for creating custom accelerators. - Sen Ma; Zeyad Aklah; David Andrews 001 (FPL, 2015)

Archborn: an open source tool for automated generation of chip heterogeneous multiprocessor architectures. - Sen Ma; Hongyuan Ding; Miaoqing Huang; David Andrews 001 (ReConFig, 2015)

Run time interpretation for creating custom accelerators. - Sen Ma; Zeyad Aklah; David Andrews 001 (DATE, 2016)

Just In Time Assembly of Accelerators. - Sen Ma; Zeyad Aklah; David Andrews 001 (FPGA, 2016)

OOGen: An Automated Generation Tool for Custom MPSoC Architectures Based on Object-Oriented Programming Methods. - Hongyuan Ding; Sen Ma; Miaoqing Huang; David Andrews 001 (IPDPS Workshops, 2016)

Breeze computing: A just in time (JIT) approach for virtualizing FPGAs in the cloud. - Sen Ma; David Andrews 001; Shanyuan Gao; Jaime Cummins (ReConFig, 2016)

Programming models for reconfigurable manycore systems. - David Andrews 001; Marco Platzner (ReCoSoC, 2016)

A Dynamic Overlay Supporting Just-In-Time Assembly to Construct Customized Hardware Accelerators. - Zeyad Aklah; Sen Ma; David Andrews 001 (CoRR, 2016)

FPGAVirt: A Novel Virtualization Framework for FPGAs in the Cloud. - Joel Mandebi Mbongue; Festus Hategekimana; Danielle Tchuinkou Kwadjo; David Andrews 001; Christophe Bobda (IEEE CLOUD, 2018)

An FPGA/HMC-Based Accelerator for Resolution Proof Checking. - Tim Hansmeier; Marco Platzner; David Andrews 001 (ARC, 2018)

Enabling Transparent Acceleration of OpenCV Library Kernels on a Hybrid Memory Cube Computer. - Md Jubaer Hossain Pantho; Joel Mandebi Mbongue; Christophe Bobda; David Andrews 001; Marjan Asadinia (FCCM, 2018)

Transparent Acceleration of Image Processing Kernels on FPGA-Attached Hybrid Memory Cube Computers. - Md Jubaer Hossain Pantho; Joel Mandebi Mbongue; Christophe Bobda; David Andrews 001 (FPT, 2018)

A Library of FSM-based Floating-Point Arithmetic Functions on FPGAs. - Atiyehsadat Panahi; Keaten Stokke; David Andrews 001 (ReConFig, 2019)

An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology. - Tim Hansmeier; Marco Platzner; Md Jubaer Hossain Pantho; David Andrews 001 (J. Signal Process. Syst., 2019)

FPGA-Based Gesture Recognition with Capacitive Sensor Array using Recurrent Neural Networks. - Haoyan Liu; Atiyehsadat Panahi; David Andrews 001; Alexander Nelson 001 (FCCM, 2020)

SPAR-2: A SIMD Processor Array for Machine Learning in IoT Devices. - Suhail Basalama; Atiyehsadat Panahi; Ange-Thierry Ishimwe; David Andrews 001 (ICDIS, 2020)

An FPGA-Based Upper-Limb Rehabilitation Device for Gesture Recognition and Motion Evaluation Using Multi-Task Recurrent Neural Networks. - Haoyan Liu; Atiyehsadat Panahi; David Andrews 001; Alexander Nelson 001 (FPT, 2020)

A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications. - Atiyehsadat Panahi; Suhail Basalama; Ange-Thierry Ishimwe; Joel Mandebi Mbongue; David Andrews 001 (FPL, 2021)

Power-based Side Channel Attack Analysis on PQC Algorithms. - Tendayi Kamucheka; Michael Fahr; Tristen Teague; Alexander Nelson 001; David Andrews 001; Miaoqing Huang (IACR Cryptol. ePrint Arch., 2021)

A Runtime Programmable Accelerator for Convolutional and Multilayer Perceptron Neural Networks on FPGA. - Ehsan Kabir; Arpan Poudel; Zeyad Aklah; Miaoqing Huang; David Andrews 001 (ARC, 2022)

High-Rate Machine Learning for Forecasting Time-Series Signals. - Atiyehsadat Panahi; Ehsan Kabir; Austin R. J. Downey; David Andrews 001; Miaoqing Huang; Jason D. Bakos (FCCM, 2022)

A Masked Pure-Hardware Implementation of Kyber Cryptographic Algorithm. - Tendayi Kamucheka; Alexander Nelson 001; David Andrews 001; Miaoqing Huang (IACR Cryptol. ePrint Arch., 2022)

Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays. - M. D. Arafat Kabir; Joshua Hollis; Atiyehsadat Panahi; Jason D. Bakos; Miaoqing Huang; David Andrews 001 (FCCM, 2023)

Accelerating LSTM-Based High-Rate Dynamic System Models. - Ehsan Kabir; Daniel Coble; Joud N. Satme; Austin R. J. Downey; Jason D. Bakos; David Andrews 001; Miaoqing Huang (FPL, 2023)

FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ? - M. D. Arafat Kabir; Ehsan Kabir; Joshua Hollis; Eli Levy-Mackay; Atiyehsadat Panahi; Jason D. Bakos; Miaoqing Huang; David Andrews 001 (FPL, 2023)

The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators. - M. D. Arafat Kabir; Tendayi Kamucheka; Nathaniel Fredricks; Joel Mandebi; Jason D. Bakos; Miaoqing Huang; David Andrews 001 (FCCM, 2024)

Ph.D. Project: A Compiler-Driven Approach to HW/SW Co-Design of Deep-Learning Accelerators. - Tendayi Kamucheka; David Andrews 001 (FCCM, 2024)

IMAGine: An In-Memory Accelerated GEMV Engine Overlay. - M. D. Arafat Kabir; Tendayi Kamucheka; Nathaniel Fredricks; Joel Mandebi; Jason D. Bakos; Miaoqing Huang; David Andrews 001 (FPL, 2024)

Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs. - Ehsan Kabir; M. D. Arafat Kabir; Austin R. J. Downey; Jason D. Bakos; David Andrews 001; Miaoqing Huang (ICFPT, 2024)

ProTEA: Programmable Transformer Encoder Acceleration on FPGA. - Ehsan Kabir; Jason D. Bakos; David Andrews 001; Miaoqing Huang (SC Workshops, 2024)

A Runtime-Adaptive Transformer Neural Network Accelerator on FPGAs. - Ehsan Kabir; Austin R. J. Downey; Jason D. Bakos; David Andrews 001; Miaoqing Huang (CoRR, 2024)

Optimized Coding and Parameter Selection for Efficient FPGA Design of Attention Mechanisms. - Ehsan Kabir; Austin R. J. Downey; Jason D. Bakos; David Andrews 001; Miaoqing Huang (FCCM, 2025)

N-TORC: Native Tensor Optimizer for Real-Time Constraints. - Suyash Vardhan Singh; Iftakhar Ahmad; David Andrews 001; Miaoqing Huang; Austin R. J. Downey; Jason D. Bakos (FCCM, 2025)

Resource Scheduling for Real-Time Machine Learning. - Suyash Vardhan Singh; Iftakhar Ahmad; David Andrews 001; Miaoqing Huang; Austin R. J. Downey; Jason D. Bakos (FPGA, 2025)