Implementing Graphics Shaders Using FPGAs. - David B. Thomas; Wayne Luk (FPL, 2004)

Pipelining designs with loop-carried dependencies. - Henry Styles; David B. Thomas; Wayne Luk (FPT, 2004)

High Quality Uniform Random Number Generation Through LUT Optimised Linear Recurrences. - David B. Thomas; Wayne Luk (FPT, 2005)

High quality uniform random number generation for massively parallel simulations in FPGA. - David B. Thomas; Wayne Luk (ReConFig, 2005)

Efficient Hardware Generation of Random Variates with Arbitrary Distributions. - David B. Thomas; Wayne Luk (FCCM, 2006)

Hardware architectures for Monte-Carlo based financial simulations. - David B. Thomas; Jacob A. Bower; Wayne Luk (FPT, 2006)

A Reconfigurable Simulation Framework for Financial Computation. - Jacob A. Bower; David B. Thomas; Wayne Luk; Oskar Mencer (ReConFig, 2006)

Reconfigurable Hardware Acceleration of Canonical Graph Labelling. - David B. Thomas; Wayne Luk; Michael Stumpf (ARC, 2007)

Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo Simulations. - David B. Thomas; Jacob A. Bower; Wayne Luk (ASAP, 2007)

Sampling from the Multivariate Gaussian Distribution using Reconfigurable Hardware. - David B. Thomas; Wayne Luk (FCCM, 2007)

A Domain Specific Language for Reconfigurable Path-based Monte Carlo Simulations. - David B. Thomas; Wayne Luk (FPT, 2007)

Gaussian random number generators. - David B. Thomas; Wayne Luk; Philip Heng Wai Leong; John D. Villasenor (ACM Comput. Surv., 2007)

Non-uniform random number generation through piecewise linear approximations. - David B. Thomas; Wayne Luk (IET Comput. Digit. Tech., 2007)

High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices. - David B. Thomas; Wayne Luk (J. VLSI Signal Process., 2007)

An FPGA run-time parameterisable Log-Normal Random Number Generator. - Pedro Echeverría; David B. Thomas; Marisa López-Vallejo; Wayne Luk (ARC, 2008)

Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models. - Qiwei Jin; David B. Thomas; Wayne Luk; Benjamin Cope (ARC, 2008)

Resource efficient generators for the floating-point uniform and exponential distributions. - David B. Thomas; Wayne Luk (ASAP, 2008)

Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation. - David B. Thomas; Wayne Luk (FCCM, 2008)

FPGA-optimised high-quality uniform random number generators. - David B. Thomas; Wayne Luk (FPGA, 2008)

Sampling from the exponential distribution using independent Bernoulli variates. - David B. Thomas; Wayne Luk (FPL, 2008)

Estimation of sample mean and variance for Monte-Carlo simulations. - David B. Thomas; Wayne Luk (FPT, 2008)

Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware. - David B. Thomas; Wayne Luk (ACM Trans. Reconfigurable Technol. Syst., 2008)

FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks. - David B. Thomas; Wayne Luk (FCCM, 2009)

Accelerating Quadrature Methods for Option Valuation. - Anson H. T. Tse; David B. Thomas; Wayne Luk (FCCM, 2009)

A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation. - David B. Thomas; Lee W. Howes; Wayne Luk (FPGA, 2009)

Exploring reconfigurable architectures for explicit finite difference option pricing models. - Qiwei Jin; David B. Thomas; Wayne Luk (FPL, 2009)

FPGA Accelerated Low-Latency Market Data Feed Processing. - Gareth W. Morris; David B. Thomas; Wayne Luk (Hot Interconnects, 2009)

Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models. - Qiwei Jin; David B. Thomas; Wayne Luk; Benjamin Cope (ACM Trans. Reconfigurable Technol. Syst., 2009)

An FPGA-specific algorithm for direct generation of multi-variate Gaussian random numbers. - David B. Thomas; Wayne Luk (ASAP, 2010)

FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers. - David B. Thomas; Wayne Luk (FPL, 2010)

Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options. - Anson H. T. Tse; David B. Thomas; Kuen Hung Tsoi; Wayne Luk (FPL, 2010)

Comparing performance and energy efficiency of FPGAs and GPUs for high productivity computing. - Brahim Betkaoui; David B. Thomas; Wayne Luk (FPT, 2010)

Dynamic scheduling Monte-Carlo framework for multi-accelerator heterogeneous clusters. - Anson H. T. Tse; David B. Thomas; Kuen Hung Tsoi; Wayne Luk (FPT, 2010)

Efficient reconfigurable design for pricing asian options. - Anson H. T. Tse; David B. Thomas; Kuen Hung Tsoi; Wayne Luk (SIGARCH Comput. Archit. News, 2010)

On Comparing Financial Option Price Solvers on FPGA. - Qiwei Jin; Wayne Luk; David B. Thomas (FCCM, 2011)

Unifying Finite Difference Option-Pricing for Hardware Acceleration. - Qiwei Jin; Wayne Luk; David B. Thomas (FPL, 2011)

A framework for FPGA acceleration of large graph problems: Graphlet counting case study. - Brahim Betkaoui; David B. Thomas; Wayne Luk; Natasa Przulj (FPT, 2011)

Management and programming of reconfigurable hardware resources. - David B. Thomas (2011)

Multi-level Customisation Framework for Curve Based Monte Carlo Financial Simulations. - Qiwei Jin; Diwei Dong; Anson H. T. Tse; Gary Chun Tak Chow; David B. Thomas; Wayne Luk; Stephen Weston (ARC, 2012)

Optimising Performance of Quadrature Methods with Reduced Precision. - Anson H. T. Tse; Gary C. T. Chow; Qiwei Jin; David B. Thomas; Wayne Luk (ARC, 2012)

A Reconfigurable Computing Approach for Efficient and Scalable Parallel Graph Exploration. - Brahim Betkaoui; Yu Wang 002; David B. Thomas; Wayne Luk (ASAP, 2012)

A mixed precision Monte Carlo methodology for reconfigurable accelerator systems. - Gary Chun Tak Chow; Anson Hong Tak Tse; Qiwei Jin; Wayne Luk; Philip Heng Wai Leong; David B. Thomas (FPGA, 2012)

Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study. - Brahim Betkaoui; Yu Wang 002; David B. Thomas; Wayne Luk (FPL, 2012)

Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGA. - Gordon Inggs; David B. Thomas; Simon Winberg (FPL, 2012)

Optimising explicit finite difference option pricing for dynamic constant reconfiguration. - Qiwei Jin; Tobias Becker; Wayne Luk; David B. Thomas (FPL, 2012)

A Domain Specific Language and Toolchain for OpenCV Runtime Binary Acceleration Using GPU. - Takaaki Miyajima; David B. Thomas; Hideharu Amano (ICNC, 2012)

Design Exploration of Quadrature Methods in Option Pricing. - Anson H. T. Tse; David B. Thomas; Wayne Luk (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Hardware Acceleration of Matrix Multiplication over Small Prime Finite Fields. - Shane T. Fleming; David B. Thomas (ARC, 2013)

Parallel Generation of Gaussian Random Numbers Using the Table-Hadamard Transform. - David B. Thomas (FCCM, 2013)

FPGA based control for real time systems. - Shane T. Fleming; David B. Thomas (FPL, 2013)

A fully pipelined FPGA architecture for stochastic simulation of chemical systems. - David B. Thomas; Hideharu Amano (FPL, 2013)

A Heterogeneous Computing Framework for Computational Finance. - Gordon Inggs; David B. Thomas; Wayne Luk (ICPP, 2013)

Scalable XML Query Processing using Parallel Pushdown Transducers. - Peter Ogden; David B. Thomas; Peter R. Pietzuch (Proc. VLDB Endow., 2013)

Customisable architectures for the set covering problem. - Liucheng Guo; David B. Thomas; Wayne Luk (SIGARCH Comput. Archit. News, 2013)

The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures. - David B. Thomas; Wayne Luk (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Multiplierless Algorithm for Multivariate Gaussian Random Number Generation in FPGAs. - David B. Thomas; Wayne Luk (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Automated Framework for General-Purpose Genetic Algorithms in FPGAs. - Liucheng Guo; David B. Thomas; Wayne Luk (EvoApplications, 2014)

Compiling Higher Order Functional Programs to Composable Digital Hardware. - Eduardo Aguilar-Pelaez; Samuel Bayliss; Alex I. Smith; Felix Winterstein; Dan R. Ghica; David B. Thomas; George A. Constantinides (FCCM, 2014)

FPGA Gaussian Random Number Generators with Guaranteed Statistical Accuracy. - David B. Thomas (FCCM, 2014)

Heterogeneous Heartbeats: A framework for dynamic management of Autonomous SoCs. - Shane T. Fleming; David B. Thomas (FPL, 2014)

Area implications of memory partitioning for high-level synthesis on FPGAs. - Luca Gallo; Alessandro Cilardo; David B. Thomas; Samuel Bayliss; George A. Constantinides (FPL, 2014)

Automated framework for FPGA-based parallel genetic algorithms. - Liucheng Guo; David B. Thomas; Ce Guo; Wayne Luk (FPL, 2014)

Is high level synthesis ready for business? A computational finance case study. - Gordon Inggs; Shane T. Fleming; David B. Thomas; Wayne Luk (FPT, 2014)

Low-latency option pricing using systolic binomial trees. - Aryan Tavakkoli; David B. Thomas (FPT, 2014)

A Domain Specific Approach to Heterogeneous Computing: From Availability to Accessibility. - Gordon Inggs; David B. Thomas; Wayne Luk (CoRR, 2014)

An Automatic Mixed Software Hardware Pipeline Builder for CPU-FPGA Platforms. - Takaaki Miyajima; David B. Thomas; Hideharu Amano (CoRR, 2014)

A General-Purpose Method for Faithfully Rounded Floating-Point Function Approximation in FPGAs. - David B. Thomas (ARITH, 2015)

Transparent linking of compiled software and synthesized hardware. - David B. Thomas; Shane T. Fleming; George A. Constantinides; Dan R. Ghica (DATE, 2015)

Pipelined Genetic Propagation. - Liucheng Guo; Ce Guo; David B. Thomas; Wayne Luk (FCCM, 2015)

System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System. - Shane T. Fleming; David B. Thomas; George A. Constantinides; Dan R. Ghica (FPGA, 2015)

PushPush: Seamless integration of hardware and software objects via function calls over AXI. - Shane T. Fleming; Ivan Beretta; David B. Thomas; George A. Constantinides; Dan R. Ghica (FPL, 2015)

Recursive pipelined genetic propagation for bilevel optimisation. - Shengjia Shao; Liucheng Guo; Ce Guo; Thomas C. P. Chau; David B. Thomas; Wayne Luk; Stephen Weston (FPL, 2015)

SysAlloc: A hardware manager for dynamic memory allocation in heterogeneous systems. - Zeping Xue; David B. Thomas (FPL, 2015)

Seeing Shapes in Clouds: On the Performance-Cost trade-off for Heterogeneous Infrastructure-as-a-Service. - Gordon Inggs; David B. Thomas; George A. Constantinides; Wayne Luk (CoRR, 2015)

An Efficient, Automatic Approach to High Performance Heterogeneous Computing. - Gordon Inggs; David B. Thomas; Wayne Luk (CoRR, 2015)

A general-purpose framework for FPGA-accelerated genetic algorithms. - Liucheng Guo; Andreea-Ingrid Funie; Zhongliu Xie; David B. Thomas; Wayne Luk (Int. J. Bio Inspired Comput., 2015)

Courier: A Toolchain for Application Acceleration on Heterogeneous Platforms. - Takaaki Miyajima; David B. Thomas; Hideharu Amano (IPSJ Trans. Syst. LSI Des. Methodol., 2015)

A Toolchain for Dynamic Function Off-load on CPU-FPGA Platforms. - Takaaki Miyajima; David B. Thomas; Hideharu Amano (J. Inf. Process., 2015)

Parallel Genetic Algorithms on Multiple FPGAs. - Liucheng Guo; Andreea-Ingrid Funie; David B. Thomas; Haohuan Fu; Wayne Luk (SIGARCH Comput. Archit. News, 2015)

The Table-Hadamard GRNG: An Area-Efficient FPGA Gaussian Random Number Generator. - David B. Thomas (ACM Trans. Reconfigurable Technol. Syst., 2015)

Synthesisable recursion for C++ HLS tools. - David B. Thomas (ASAP, 2016)

StitchUp: automatic control flow protection for high level synthesis circuits. - Shane T. Fleming; David B. Thomas (DAC, 2016)

Increasing Network Size and Training Throughput of FPGA Restricted Boltzmann Machines Using Dropout. - Jiang Su; David B. Thomas; Peter Y. K. Cheung (FCCM, 2016)

SynADT: Dynamic Data Structures in High Level Synthesis. - Zeping Xue; David B. Thomas (FCCM, 2016)

AT-GIS: Highly Parallel Spatial Query Processing with Associative Transducers. - Peter Ogden; David B. Thomas; Peter R. Pietzuch (SIGMOD Conference, 2016)

Neural Network Based Reinforcement Learning Acceleration on FPGA Platforms. - Jiang Su; Jianxiong Liu; David B. Thomas; Peter Y. K. Cheung (SIGARCH Comput. Archit. News, 2016)

Using Runahead Execution to Hide Memory Latency in High Level Synthesis. - Shane T. Fleming; David B. Thomas (FCCM, 2017)

Programming Model to Develop Supercomputer Combinatorial Solvers. - Ghaith Tarawneh; Andrey Mokhov; Matthew Naylor; Alex Rast; Simon W. Moore; David B. Thomas; Alex Yakovlev; Andrew D. Brown (ICPP Workshops, 2017)

Distributed Event-Based Computing. - Andrew D. Brown; David B. Thomas; Jeff Reeve; Ghaith Tarawneh; Alessandro de Gennaro; Andrey Mokhov; Matthew Naylor; Tom Kazmierski (PARCO, 2017)

A Domain Specific Approach to High Performance Heterogeneous Computing. - Gordon Inggs; David B. Thomas; Wayne Luk (IEEE Trans. Parallel Distributed Syst., 2017)

Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic. - Jiang Su; Nicholas J. Fraser; Giulio Gambardella; Michaela Blott; Gianluca Durelli; David B. Thomas; Philip Heng Wai Leong; Peter Y. K. Cheung (ARC, 2018)

Redundancy-Reduced MobileNet Acceleration on Reconfigurable Logic for ImageNet Classification. - Jiang Su; Julian Faraone; Junyi Liu; Yiren Zhao; David B. Thomas; Philip Heng Wai Leong; Peter Y. K. Cheung (ARC, 2018)

Injecting FPGA Configuration Faults in Parallel. - Shane T. Fleming; David B. Thomas (FPT, 2018)

Accelerating Top-k ListNet Training for Ranking Using FPGA. - Qiang Li; Shane T. Fleming; David B. Thomas; Peter Y. K. Cheung (FPT, 2018)

A High-Level Design Framework for the Automatic Generation of High-Throughput Systolic Binomial-Tree Solvers. - Aryan Tavakkoli; David B. Thomas (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Compile-Time Generation of Custom-Precision Floating-Point IP using HLS Tools. - David B. Thomas (ARITH, 2019)

Formalizing Loop-Carried Dependencies in Coq for High-Level Synthesis. - Florian Faissole; George A. Constantinides; David B. Thomas (FCCM, 2019)

Templatised Soft Floating-Point for High-Level Synthesis. - David B. Thomas (FCCM, 2019)

Accelerating Position-Aware Top-k ListNet for Ranking Under Custom Precision Regimes. - Qiang Li; Erwei Wang; Shane T. Fleming; David B. Thomas; Peter Y. K. Cheung (FPL, 2019)

Tinsel: A Manythread Overlay for FPGA Clusters. - Matthew Naylor; Simon W. Moore; David B. Thomas (FPL, 2019)

POETS: Distributed Event-Based Computing - Scaling Behaviour. - Andrew D. Brown; Mark Vousden; Alex Rast; Graeme M. Bragg; David B. Thomas; Jonny Beaumont; Matthew Naylor; Andrey Mokhov (PARCO, 2019)

Termination detection for fine-grained message-passing architectures. - Matthew Naylor; Simon W. Moore; Andrey Mokhov; David B. Thomas; Jonathan R. Beaumont; Shane T. Fleming; A. Theodore Markettos; Thomas Bytheway; Andrew D. Brown (ASAP, 2020)

Exploring performance enhancement of event-driven processor networks. - Tim Todman; David B. Thomas; Wayne Luk (FPT, 2020)

A Hardware/Application Overlay Model for Large-Scale Neuromorphic Simulation. - Alexander Rast; Mahyar Shahsavari; Graeme M. Bragg; Mark Vousden; David B. Thomas; Andrew D. Brown (IJCNN, 2020)

Neuromorphic Design Using Reward-based STDP Learning on Event-Based Reconfigurable Cluster Architecture. - Mahyar Shahsavari; David B. Thomas; Andrew D. Brown; Wayne Luk (ICONS, 2021)

General hardware multicasting for fine-grained message-passing architectures. - Matthew Naylor; Simon W. Moore; David B. Thomas; Jonathan R. Beaumont; Shane T. Fleming; Mark Vousden; A. Theodore Markettos; Thomas Bytheway; Andrew D. Brown (PDP, 2021)

Non-deterministic event brokered computing. - Andrew Brown; Tim Todman; Wayne Luk; David B. Thomas; Mark Vousden; Graeme M. Bragg; Jonny Beaumont; Simon W. Moore; Alex Yakovlev; Ashur Rafiev (HEART, 2022)

Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture. - Ashur Rafiev; Alex Yakovlev; Ghaith Tarawneh; Matthew Naylor; Simon W. Moore; David B. Thomas; Graeme M. Bragg; Mark Vousden; Andrew D. Brown (IET Comput. Digit. Tech., 2022)

Practical Distributed Implementation of Very Large Scale Petri Net Simulations. - Ashur Rafiev; Jordan Morris; Fei Xia 001; Alex Yakovlev; Matthew Naylor; Simon W. Moore; David B. Thomas; Graeme M. Bragg; Mark Vousden; Andrew Brown (Trans. Petri Nets Other Model. Concurr., 2022)

An Event-Driven Approach To Genotype Imputation On A Custom RISC-V FPGA Cluster. - Jordan Morris; Ashur Rafiev; Graeme M. Bragg; Mark Vousden; David B. Thomas; Alex Yakovlev; Andrew Brown (CoRR, 2023)

Event-based high throughput computing: A series of case studies on a massively parallel softcore machine. - Mark Vousden; Jordan Morris; Graeme McLachlan Bragg; Jonathan Beaumont; Ashur Rafiev; Wayne Luk; David B. Thomas; Andrew D. Brown (IET Comput. Digit. Tech., 2023)

POETS: An Event-driven Approach to Dissipative Particle Dynamics: Implementing a Massively Compute-intensive Problem on a Novel Hard/Software Architecture. - Andrew D. Brown; Jonathan R. Beaumont; David B. Thomas; Julian C. Shillcock; Matthew Naylor; Graeme M. Bragg; Mark Vousden; Simon W. Moore; Shane T. Fleming (ACM Trans. Parallel Comput., 2023)

Advancements in spiking neural network communication and synchronization techniques for event-driven neuromorphic systems. - Mahyar Shahsavari; David B. Thomas; Marcel van Gerven; Andrew D. Brown; Wayne Luk (Array, 2023)

An Event-Driven Approach to Genotype Imputation on a Custom RISC-V Cluster. - Jordan Morris; Ashur Rafiev; Graeme M. Bragg; Mark L. Vousden; David B. Thomas; Alex Yakovlev; Andrew D. Brown (IEEE ACM Trans. Comput. Biol. Bioinform., 2024)