JITPCB. - Jonathan Bachrach; David Biancolin; Austin Buchan; Duncan W. Haldane; Richard Lin (IROS, 2016)

Fine-Grained Interconnect Synthesis. - Alex Rodionov; David Biancolin; Jonathan Rose (ACM Trans. Reconfigurable Technol. Syst., 2016)

A Hardware Accelerator for Computing an Exact Dot Product. - Jack Koenig; David Biancolin; Jonathan Bachrach; Krste Asanovic (ARITH, 2017)

DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of Cycles. - Donggyu Kim; Christopher Celio; Sagar Karandikar; David Biancolin; Jonathan Bachrach; Krste Asanovic (FPL, 2018)

FASED: FPGA-Accelerated Simulation and Evaluation of DRAM. - David Biancolin; Sagar Karandikar; Donggyu Kim; Jack Koenig; Andrew Waterman; Jonathan Bachrach; Krste Asanovic (FPGA, 2019)

Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes. - Albert Magyar; David Biancolin; John Koenig; Sanjit Seshia; Jonathan Bachrach; Krste Asanovic (ICCAD, 2019)

FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud. - Sagar Karandikar; Howard Mao; Donggyu Kim; David Biancolin; Alon Amid; Dayeol Lee; Nathan Pemberton; Emmanuel Amaro; Colin Schmidt 001; Aditya Chopra; Qijing Huang 001; Kyle Kovacs; et al. (IEEE Micro, 2019)

Invited: Chipyard - An Integrated SoC Research and Implementation Environment. - Alon Amid; David Biancolin; Abraham Gonzalez; Daniel Grubb; Sagar Karandikar; Harrison Liew; Albert Magyar; Howard Mao; Albert J. Ou; Nathan Pemberton; Paul Rigge; Colin Schmidt 001; et al. (DAC, 2020)

Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs. - Alon Amid; David Biancolin; Abraham Gonzalez; Daniel Grubb; Sagar Karandikar; Harrison Liew; Albert Magyar; Howard Mao; Albert J. Ou; Nathan Pemberton; Paul Rigge; Colin Schmidt 001; et al. (IEEE Micro, 2020)

Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim. - David Biancolin; Albert Magyar; Sagar Karandikar; Alon Amid; Borivoje Nikolic; Jonathan Bachrach; Krste Asanovic (IEEE Micro, 2021)

Automated, FPGA-Based Hardware Emulation of Dynamic Frequency Scaling - David Biancolin (2021)

Simulator Independent Coverage for RTL Hardware Languages. - Kevin Laeufer; Vighnesh Iyer; David Biancolin; Jonathan Bachrach; Borivoje Nikolic; Koushik Sen (ASPLOS (3), 2023)