A reusable BIST with software assisted repair technology for improved memory and IO debug, validation and test time. - Bruce Querbach; Rahul Khanna; David Blankenbeckler; Yulan Zhang; Ronald T. Anderson; David G. Ellis; Zale T. Schoenborn; Sabyasachi Deyati; Patrick Chiang 001 (ITC, 2014)

Platform IO and system memory test using L3 cache based test (CBT) and parallel execution of CPGC Intel BIST engine. - Bruce Querbach; Tan Peter Yanyang; Lovelace Van; David Blankenbeckler; Rahul Khanna; Sudeep Puligundla; Patrick Chiang 001 (ITC, 2015)

Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC. - Bruce Querbach; Rahul Khanna; Sudeep Puligundla; David Blankenbeckler; Joseph Crop; Patrick Yin Chiang (IEEE Des. Test, 2016)