An FPGA-based implementation of the MINRES algorithm. - David Boland; George A. Constantinides (FPL, 2008)

Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods. - David Boland; George A. Constantinides (ARC, 2010)

Automated Precision Analysis: A Polynomial Algebraic Approach. - David Boland; George A. Constantinides (FCCM, 2010)

The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA. - Christophe Le Lann; David Boland; George A. Constantinides (ARC, 2011)

Bounding Variable Values and Round-Off Effects Using Handelman Representations. - David Boland; George A. Constantinides (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Optimizing memory bandwidth use and performance for matrix-vector multiplication in iterative methods. - David Boland; George A. Constantinides (ACM Trans. Reconfigurable Technol. Syst., 2011)

FPGA Paranoia: Testing Numerical Properties of FPGA Floating Point IP-Cores. - Xuan You Tan; David Boland; George A. Constantinides (ARC, 2012)

A scalable approach for automated precision analysis. - David Boland; George A. Constantinides (FPGA, 2012)

Precision analysis for hardware acceleration of numerical algorithms. - David Boland (2012)

Accuracy-Performance Tradeoffs on an FPGA through Overclocking. - Kan Shi; David Boland; George A. Constantinides (FCCM, 2013)

Word-length optimization beyond straight line code. - David Boland; George A. Constantinides (FPGA, 2013)

Revisiting the reduction circuit: A case study for simultaneous architecture and precision optimisation. - David Boland; George A. Constantinides (FPT, 2013)

Overclocking datapath for latency-error tradeoff. - Kan Shi; David Boland; George A. Constantinides (ISCAS, 2013)

A Scalable Precision Analysis Framework. - David Boland; George A. Constantinides (IEEE Trans. Multim., 2013)

Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs. - Kan Shi; David Boland; Edward A. Stott; Samuel Bayliss; George A. Constantinides (DAC, 2014)

Efficient FPGA implementation of digit parallel online arithmetic operators. - Kan Shi; David Boland; George A. Constantinides (FPT, 2014)

Imprecise Datapath Design: An Overclocking Approach. - Kan Shi; David Boland; George A. Constantinides (ACM Trans. Reconfigurable Technol. Syst., 2015)

Reducing Memory Requirements for High-Performance and Numerically Stable Gaussian Elimination. - David Boland (FPGA, 2016)

Dynamic bitwidth assignment for efficient dot products. - Simon Joel Schmidt; David Boland (FPL, 2017)

FPGA acceleration of multilevel ORB feature extraction for computer vision. - Josh Weberruss; Lindsay Kleeman; David Boland; Tom Drummond (FPL, 2017)

FPGA-based layered/enhanced ACO-OFDM transmitter. - Qibing Wang; Binhuang Song; Bill Corcoran; David Boland; Leimeng Zhuang; Yiwei Xie; Arthur James Lowery (OFC, 2017)

FPGA Fastfood - A High Speed Systolic Implementation of a Large Scale Online Kernel Method. - Sean Fox; David Boland; Philip Heng Wai Leong (FPGA, 2018)

Customizing Low-Precision Deep Neural Networks for FPGAs. - Julian Faraone; Giulio Gambardella; Nicholas J. Fraser; Michaela Blott; Philip H. W. Leong; David Boland (FPL, 2018)

Simultaneous Inference and Training Using On-FPGA Weight Perturbation Techniques. - Siddhartha 003; Steven J. E. Wilton; David Boland; Barry Flower; Perry Blackmore; Philip H. W. Leong (FPT, 2018)

Real-time FPGA-based Anomaly Detection for Radio Frequency Signals. - Duncan J. M. Moss; David Boland; Peyam Pourbeik; Philip Heng Wai Leong (ISCAS, 2018)

Long Short-Term Memory for Radio Frequency Spectral Prediction and its Real-Time FPGA Implementation. - Siddhartha 003; Yee Hui Lee; Duncan J. M. Moss; Julian Faraone; Perry Blackmore; Daniel Salmond; David Boland; Philip H. W. Leong (MILCOM, 2018)

Training Deep Neural Networks in Low-Precision with High Accuracy Using FPGAs. - Sean Fox; Julian Faraone; David Boland; Kees A. Vissers; Philip H. W. Leong (FPT, 2019)

MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency. - Seyedramin Rasoulinezhad; Sean Fox; Hao Zhou 008; Lingli Wang; David Boland; Philip H. W. Leong (FPT, 2019)

Real-Time Automatic Modulation Classification. - Stephen Tridgell; David Boland; Philip H. W. Leong; Siddhartha 003 (FPT, 2019)

Unrolling Ternary Neural Networks. - Stephen Tridgell; Martin Kumm; Martin Hardieck; David Boland; Duncan J. M. Moss; Peter Zipf; Philip H. W. Leong (ACM Trans. Reconfigurable Technol. Syst., 2019)

A Two-Speed, Radix-4, Serial-Parallel Multiplier. - Duncan J. M. Moss; David Boland; Philip H. W. Leong (IEEE Trans. Very Large Scale Integr. Syst., 2019)

LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations. - Seyedramin Rasoulinezhad; Siddhartha 003; Hao Zhou 008; Lingli Wang; David Boland; Philip H. W. Leong (FPGA, 2020)

Real-time Automatic Modulation Classification using RFSoC. - Stephen Tridgell; David Boland; Philip H. W. Leong; Ryan Kastner; Alireza Khodamoradi; Siddhartha 003 (IPDPS Workshops, 2020)

Derivation of Respiratory Metrics in Health and Asthma. - Joseph Prinable; Peter Jones; David Boland; Alistair Lee McEwan; Cindy Thamrin (Sensors, 2020)

AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers. - Julian Faraone; Martin Kumm; Martin Hardieck; Peter Zipf; Xueyuan Liu 002; David Boland; Philip H. W. Leong (IEEE Trans. Very Large Scale Integr. Syst., 2020)

MLBlocks: FPGA Blocks for Machine Learning Applications. - Seyedramin Rasoulinezhad; David Boland; Philip H. W. Leong (FPGA, 2021)

A Block Minifloat Representation for Training Deep Neural Networks. - Sean Fox; Seyedramin Rasoulinezhad; Julian Faraone; David Boland; Philip H. W. Leong (ICLR, 2021)

FPGA Implementation of N-BEATS for Time Series Forecasting Using Block Minifloat Arithmetic. - Wenjie Zhou; Haoyan Qi; David Boland; Philip H. W. Leong (APCCAS, 2022)

Rethinking Embedded Blocks for Machine Learning Applications. - Seyedramin Rasoulinezhad; Esther Roorda; Steve Wilton; Philip H. W. Leong; David Boland (ACM Trans. Reconfigurable Technol. Syst., 2022)

Single-Batch CNN Training using Block Minifloats on FPGAs. - Chuliang Guo; Binglei Lou; Xueyuan Liu 002; David Boland; Philip H. W. Leong (FPGA, 2023)

ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration. - Kan Shi; Shuoxiang Xu; Yuhan Diao; David Boland; Yungang Bao (FPGA, 2023)

BOOST: Block Minifloat-Based On-Device CNN Training Accelerator with Transfer Learning. - Chuliang Guo; Binglei Lou; Xueyuan Liu 002; David Boland; Philip H. W. Leong; Cheng Zhuo (ICCAD, 2023)

On-Board Federated Learning in Orbital Edge Computing. - Mohammad Reza Jabbarpour; Bahman Javadi; Philip H. W. Leong; Rodrigo N. Calheiros; David Boland; Chris Butler (ICPADS, 2023)

Performance Analysis of Federated Learning in Orbital Edge Computing. - Mohammad Reza Jabbarpour; Bahman Javadi; Philip H. W. Leong; Rodrigo N. Calheiros; David Boland; Chris Butler (UCC, 2023)

A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation. - Xiangwei Li; Douglas L. Maskell; Carol Jingyi Li; Philip H. W. Leong; David Boland (ACM Trans. Reconfigurable Technol. Syst., 2023)

Fixed-point FPGA Implementation of the FFT Accumulation Method for Real-time Cyclostationary Analysis. - Carol Jingyi Li; Xiangwei Li; Binglei Lou; Craig T. Jin; David Boland; Philip H. W. Leong (ACM Trans. Reconfigurable Technol. Syst., 2023)

fSEAD: A Composable FPGA-based Streaming Ensemble Anomaly Detection Library. - Binglei Lou; David Boland; Philip H. W. Leong (ACM Trans. Reconfigurable Technol. Syst., 2023)

Hassert: Hardware Assertion-Based Verification Framework with FPGA Acceleration. - Ziqing Zhang; Weijie Weng; Yaning Li; Lijia Cai; Haoyu Wang; David Boland; Yungang Bao; Kan Shi (ASPLOS (4), 2024)

PolyLUT-Add: FPGA-based LUT Inference with Wide Inputs. - Binglei Lou; Richard Rademacher; David Boland; Philip H. W. Leong (FPL, 2024)

S$^{3}$CA: A Sparse Strip Spectral Correlation Analyzer. - Carol Jingyi Li; Richard Rademacher; David Boland; Craig T. Jin; Chad M. Spooner; Philip H. W. Leong (IEEE Signal Process. Lett., 2024)

FedOrbit: Energy Efficient Federated Learning for Orbital Edge Computing Using Block Minifloat Arithmetic. - Mohammad Reza Jabbarpour; Bahman Javadi; Philip H. W. Leong; Rodrigo N. Calheiros; David Boland (IEEE Trans. Serv. Comput., 2024)

Corvus: Efficient HW/SW Co-Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration. - Zijian Jiang; Keran Zheng; David Boland; Yungang Bao; Kan Shi (ASP-DAC, 2025)

Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA Acceleration. - Shuoxiang Xu; Zijian Jiang; Yuxin Zhang; David Boland; Yungang Bao; Kan Shi (FPGA, 2025)

Highly Parallel CNN Accelerator for RepVGG-Like Network Training on FPGAs. - Chuliang Guo; Binglei Lou; David Boland; Philip H. W. Leong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

FPGA-based Block Minifloat Training Accelerator for a Time Series Prediction Network. - Wenjie Zhou; Haoyan Qi; David Boland; Philip H. W. Leong (ACM Trans. Reconfigurable Technol. Syst., 2025)