Tester Independent Support Software System (TISSS). - L. J. Falkenstrom; David C. Keezer; A. Patterson; Robert M. Rolfe; J. Wolcott (ITC, 1985)

Multiplexing test system channels for data rates above 1 Gb/s. - David C. Keezer (ITC, 1990)

High Frequency Wafer Probing and Power Supply Resonance Effects. - S. P. Athan; David C. Keezer; J. McKinley (ITC, 1991)

Real-Time Data Comparison for GigaHertz Digital Test. - David C. Keezer (ITC, 1991)

Wafer Scale Integration: A university perspective. - Vijay K. Jain; David L. Landis; David C. Keezer; K. T. Wilson; Denny Whittaker (J. VLSI Signal Process., 1991)

MCM Test Using Available Technology. - David C. Keezer (ITC, 1992)

Calibration Techniques for a Gigahertz Test System. - David C. Keezer; R. J. Wenzel (ITC, 1992)

An Architecture for WSI Rapid Prototyping. - Vijay K. Jain; Hiroomi Hikawa; David C. Keezer (Computer, 1992)

SMAC: A Scene Matching Chip. - N. Ranganathan; Raghu Sastry; Raguveer Venkatesan; Joseph W. Yoder; David C. Keezer (ICCD, 1993)

Known Godd Die for MCMs: Enabling Technologies. - David C. Keezer (ITC, 1993)

Electrical Troubleshooting, Diagnostics, and Repair of Multichip Modules. - David C. Keezer (ITC, 1995)

Low-Cost ATE PinElectronics for Multigigabit-per-Second At-Speed Test. - David C. Keezer; R. J. Wenzel (ITC, 1997)

A Low-Cost Massively-Parallel Interconnect Test Method for MCM Substrates. - K. E. Newman; David C. Keezer (ITC, 1997)

Improved sensitivity for parallel test of substrate interconnections. - David C. Keezer; K. E. Newman; John S. Davis (ITC, 1998)

Alternative interface methods for testing high speed bidirectional signals. - David C. Keezer; Q. Zhou (ITC, 1998)

A high throughput test methodology for MCM substrates. - Bruce C. Kim; David C. Keezer; Abhijit Chatterjee (ITC, 1998)

Test support processors for enhanced testability of high performance circuits. - David C. Keezer; Q. Zhou (ITC, 1999)

Terabit-per-second automated digital testing. - David C. Keezer; Q. Zhou; C. Bair; J. Kuan; B. Poole (ITC, 2001)

Multi-Purpose Digital Test Core Utilizing Programmable Logic. - John S. Davis; David C. Keezer (ITC, 2002)

Challenges and Solutions for Multi-Gigahertz Testing. - David C. Keezer (ITC, 2002)

Multi-GigaHertz Testing Challenges and Solutions. - Karim Arabi; Klaus-Dieter Hilliges; David C. Keezer; Sassan Tabatabaei (VTS, 2002)

Application and Demonstration of a Digital Test Core: Optoelectronic Test Bed and Wafer-level Prober. - John S. Davis; David C. Keezer; Odile Liboiron-Ladouceur; Keren Bergman (ITC, 2003)

A Production-Oriented Multiplexing System for Testing above 2.5 Gbps. - David C. Keezer; Dany Minier; Marie-Christine Caron (ITC, 2003)

Modular Extension of ATE to 5 Gbps. - David C. Keezer; Dany Minier; F. Binette (ITC, 2004)

Multiplexing ATE Channels for Production Testing at 2.5 Gbps. - David C. Keezer; Dany Minier; Marie-Christine Caron (IEEE Des. Test Comput., 2004)

A 5 Gbps Wafer-Level Tester. - A. M. Majid; David C. Keezer; J. V. Karia (Asian Test Symposium, 2005)

Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL. - David C. Keezer; Carl Gray; Ashraf M. Majid; Nafeez Taher (DATE, 2005)

Implementing multi-gigahertz test systems using CMOS FPGAs and PECL components. - David C. Keezer; Carl Gray; Ashraf Majid; Nafeez Taher (ESSCIRC, 2005)

Multi-Gigahertz Testing of Wafer-Level Packaged Devices. - A. M. Majid; David C. Keezer; Jayasanker Jayabalan; Mihai Rotaru (ITC, 2006)

Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses. - David C. Keezer; Dany Minier; Patrice Ducharme (IEEE Des. Test Comput., 2006)

Method for reducing jitter in multi-gigahertz ATE. - David C. Keezer; Dany Minier; Patrice Ducharme (DATE, 2007)

Co-development of test electronics and PCI Express interface for a multi-Gbps optical switching network. - Carl Edward Gray; Odile Liboiron-Ladouceur; David C. Keezer; Keren Bergman (ITC, 2007)

Multi-GHz loopback testing using MEMs switches and SiGe logic. - David C. Keezer; Dany Minier; Patrice Ducharme; Doris Viens; Greg Flynn; John McKillop (ITC, 2007)

Variable Delay of Multi-Gigahertz Digital Signals for Deskew and Jitter-Injection Test Applications. - David C. Keezer; Dany Minier; Patrice Ducharme (DATE, 2008)

An Electronic Module for 12.8 Gbps Multiplexing and Loopback Test. - David C. Keezer; Dany Minier; Patrice Ducharme; A. M. Majid (ITC, 2008)

MEMS Switches and SiGe Logic for Multi-GHz Loopback Testing. - David C. Keezer; Dany Minier; Patrice Ducharme; Doris Viens; Greg Flynn; John McKillop (VLSI Design, 2008)

A development platform and electronic modules for automated test up to 20 Gbps. - David C. Keezer; Carl Gray; A. M. Majid; Dany Minier; Patrice Ducharme (ITC, 2009)

Stretching the limits of FPGA SerDes for enhanced ATE performance. - A. M. Majid; David C. Keezer (DATE, 2010)

An architecture for graphics processing in an FPGA (abstract only). - Marcus Dutton; David C. Keezer (FPGA, 2010)

Low-Cost 20 Gbps Digital Test Signal Synthesis Using SiGe and InP Logic. - David C. Keezer; Carl Gray; Dany Minier; Patrice Ducharme (J. Electron. Test., 2010)

Burst-Mode Transmission and Data Recovery for Multi-GHz Optical Packet Switching Network Testing. - Carl Gray; David C. Keezer; Howard Wang; Keren Bergman (Asian Test Symposium, 2011)

Two methods for 24 Gbps test signal synthesis. - David C. Keezer; Carl Edward Gray (DATE, 2011)

Multi-function multi-GHz ATE extension using state-of-the-art FPGAs. - A. M. Majid; David C. Keezer (ITC, 2011)

Extending a DWDM Optical Network Test System to 12 Gbps x4 Channels. - Carl Edward Gray; David C. Keezer (J. Electron. Test., 2011)

Multi-gigahertz arbitrary timing generator and data pattern serializer/formatter. - David C. Keezer; Te-Hui Chen; Carl Edward Gray; Hyun Woo Choi; Sungyeol Kim; Seongkwan Lee; Hosun Yoo (ITC, 2012)

Guest Editorial: Special Issue on Analog, Mixed-Signal, RF, and MEMS Testing. - Hsiu-Ming (Sherman) Chang; David C. Keezer (J. Electron. Test., 2012)

Enhanced Resolution Time-Domain Reflectometry for High Speed Channels: Characterizing Spatial Discontinuities with Non-ideal Stimulus. - Suvadeep Banerjee; Hyun Woo Choi; David C. Keezer; Abhijit Chatterjee (Asian Test Symposium, 2013)

Minimizing simultaneous switching noise at reduced power with constant-voltage power transmission lines for high-speed signaling. - Satyanarayana Telikepalli; Madhavan Swaminathan; David C. Keezer (ISQED, 2013)

Practical methods for extending ATE to 40 and 50Gbps. - David C. Keezer; Carl Edward Gray; Te-Hui Chen; Ashraf Majid (ITC, 2013)

A signature based architecture for Trojan detection. - Aderinola Gbade-Alabi; David C. Keezer; Vincent John Mooney; Axel York Poschmann; Marc Stöttinger; Kshitij Divekar (WESS, 2014)

Multi-channel testing architecture for high-speed eye-diagram using pin electronics and subsampling monobit reconstruction algorithms. - Thomas Moon; Hyun Woo Choi; David C. Keezer; Abhijit Chatterjee (VTS, 2014)

A Novel Approach to Detect Hardware Trojan Attacks on Primary Data Inputs. - Taimour Wehbe; Vincent John Mooney; David C. Keezer; Nicholas B. Parham (WESS, 2015)

An FPGA-based ATE extension module for low-cost multi-GHz memory test. - David C. Keezer; Te-Hui Chen; Thomas Moon; D. T. Stonecypher; Abhijit Chatterjee; Hyun Woo Choi; Sungyeol Kim; Hosun Yoo (ETS, 2015)

An Ultra-High-Speed Test Module and FPGA-Based Development Platform. - Te-Hui Chen; David C. Keezer (ATS, 2016)

A 40Gbps economic extension board and FPGA-based testing platform. - Te-Hui Chen; David C. Keezer (ETS, 2016)

Use of Analog Signatures for Hardware Trojan Detection. - Taimour Wehbe; Vincent John Mooney; David C. Keezer; Omer T. Inan; Abdul Qadir Javaid (FPGAworld, 2017)

Biologically inspired hierarchical structure for self-repairing FPGAs. - David C. Keezer; Jingchi Yang (ReConFig, 2017)

A chip-level security framework for assessing sensor data integrity: work-in-progress. - Taimour Wehbe; Vincent John Mooney; David C. Keezer (CODES+ISSS, 2018)

Hardware-Based Run-Time Code Integrity in Embedded Devices. - Taimour Wehbe; Vincent John Mooney III; David C. Keezer (Cryptogr., 2018)

Securing Medical Devices Against Hardware Trojan Attacks Through Analog-, Digital-, and Physiological-Based Signatures. - Taimour Wehbe; Vincent John Mooney; Omer T. Inan; David C. Keezer (J. Hardw. Syst. Secur., 2018)

A Framework for Design of Self-Repairing Digital Systems. - Jingchi Yang; David C. Keezer (ITC, 2019)

Efficient Built-In Test and Calibration of High Speed Serial I/O Systems Using Monobit Signal Acquisition. - Thomas Moon; Hyun Woo Choi; David C. Keezer; Abhijit Chatterjee (J. Electron. Test., 2019)

Experimental Evaluation of Jitter Reduction Methods for Multi-Gigahertz Test. - David C. Keezer; Dany Minier; Hongjie Li (ITC-Asia, 2023)

Characterization of Ultra-low Random Jitter Reduction Methods up to 36 GHz. - David C. Keezer; Dany Minier; Hongjie Li (ETS, 2024)

Multi-Stage Jitter-Reduction and Frequency Multiplication for 54 GHz ATE Clocks. - David C. Keezer; Dany Minier (ITC-Asia, 2024)