A 1 V 0.9 dB NF low noise amplifier for 5-6 GHz WLAN in 0.18 μm CMOS. - David Cassan; John R. Long (CICC, 2002)

A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-μm CMOS. - David Cassan; John R. Long (IEEE J. Solid State Circuits, 2003)

An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technology. - Mehrdad Ramezani; Mohamed Abdalla; Ayal Shoval; Marcus van Ierssel; Afshin Rezayee; Angus McLaren; Chris D. Holdenried; Jennifer Pham; Eric So; David Cassan; Saman Sadr (ISSCC, 2011)

A low jitter 2.7mW/Gbps 180Gb/s 12-lane transmitter in a 40nm CMOS technology. - Kamran Farzan; Mehrdad Ramezani; Angus McLaren; Roman Pahuta; Nadeesha Amarasinghe; David Cassan; Saman Sadr (ESSCIRC, 2012)

Performance of edge tap decision feedback equalization methods for wireline receivers. - Chris D. Holdenried; Ryan Bespalko; Marcus van Ierssel; Mehrdad Ramezani; David Cassan; Siamak Sarvari; Saman Sadr (NEWCAS, 2014)

A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS. - Shayan Shahramian; Behzad Dehlaghi; Joshua Liang; Ryan Bespalko; Dustin Dunwell; James Bailey 002; Bo Wang; Alireza Sharif Bakhtiar; Michael O'Farrell; Kerry Tang; Anthony Chan Carusone; David Cassan; et al. (ISSCC, 2019)

A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver. - James Bailey 002; Hossein Shakiba; Ehud Nir; Grigory Marderfeld; Peter Krotnev; Marc-Andre LaCroix; David Cassan (ISSCC, 2021)

A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver. - James Bailey 002; Hossein Shakiba; Ehud Nir; Grigory Marderfeld; Peter Krotnev; Marc-Andre LaCroix; David Cassan; Davide Tonietto (IEEE J. Solid State Circuits, 2022)