Concurrent Error Detection/Correction in the HAL MMU Chip. - David Chih-Wei Chang; Nirmal R. Saxena (FTCS, 1993)

Microarchitecture of HaL's Memory Management Unit. - David Chih-Wei Chang; David Lyon; Charles Chen; Leon Peng; Mehran Massoumi; Matthew Hakimi; Satish Iyengar; Ellen Li; Roque Remedios (COMPCON, 1995)

Fault-Tolerant Features in the HaL Memory Management Unit. - Nirmal R. Saxena; David Chih-Wei Chang; Kevin Dawallu; Jaspal Kohli; Pat Helland (IEEE Trans. Computers, 1995)

PAC DSP Core and Application Processors. - David Chih-Wei Chang; I-Tao Liao; Jenq Kuen Lee; Wen-Feng Chen; Shau-Yin Tseng; Chein-Wei Jen (ICME, 2006)

Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools. - David Chih-Wei Chang; Tay-Jyi Lin; Chung-Ju Wu; Jenq Kuen Lee; Yuan-Hua Chu; An-Yeu Wu (J. Signal Process. Syst., 2011)