Optimizing LUT-Based Quantum Circuit Synthesis Using Relative Phase Boolean Operations. - David Clarino; Naoya Asada; Shigeru Yamashita (ICCAD, 2023)

Using S Gates and Relative Phase Toffoli Gates to Improve T-Count in Quantum Boolean Circuits. - David Clarino; Shohei Kuroda; Shigeru Yamashita (ISMVL, 2023)

Utilizing Don't-Cares to Minimize CNOTs in Synthesizing NNA Compliant Quantum Circuits. - David Clarino; Kyouhei Seino; Atsushi Matsuo; Shigeru Yamashita (QCE, 2024)

Reducing T-Count in Quantum Circuits Using Alternate Forms of the Relative Phase Toffoli Gate. - David Clarino; Shohei Kuroda; Shigeru Yamashita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)

Leveraging Different Boolean Function Decompositions to Reduce T-Count in LUT-Based Quantum Circuit Synthesis. - David Clarino; Naoya Asada; Atsushi Matsuo; Shigeru Yamashita (IEICE Trans. Inf. Syst., 2025)