An alternative to unify performance and reliability analysis of industrial applications. - Lenin Lemus; David de Andrés; Pedro J. Gil (ESM, 2000)

INERTE: Integrated NExus-Based Real-Time Fault Injection Tool for Embedded Systems. - Pedro Yuste; David de Andrés; Lenin Lemus; Juan José Serrano; Pedro J. Gil (DSN, 2003)

Codesign methodology for computer vision applications. - José Albaladejo; David de Andrés; Lenin Lemus; Joaquim Salvi (Microprocess. Microsystems, 2004)

Fast Run-Time Reconfiguration for SEU Injection. - David de Andrés; José Albaladejo; Lenin Lemus; Pedro J. Gil (EDCC, 2005)

Run-Time Reconfiguration for Emulating Transient Faults in VLSI Systems. - David de Andrés; Juan-Carlos Ruiz-Garcia 001; Daniel Gil; Pedro J. Gil (DSN, 2006)

Fast Emulation of Permanent Faults in VLSI Systems. - David de Andrés; Juan-Carlos Ruiz-Garcia 001; Daniel Gil; Pedro J. Gil (FPL, 2006)

FADES: a fault emulation tool for fast dependability assessment. - David de Andrés; Juan-Carlos Ruiz-Garcia 001; Daniel Gil; Pedro J. Gil (FPT, 2006)

Dependability Assessment for the Selection of Embedded Cores. - David de Andrés; Juan-Carlos Ruiz-Garcia 001; Daniel Gil; Pedro J. Gil (EDCC, 2008)

Generic Design and Automatic Deployment of NMR Strategies on HW Cores. - Juan-Carlos Ruiz-Garcia 001; David de Andrés; Sara Blanc; Pedro J. Gil (PRDC, 2008)

Fault Emulation for Dependability Evaluation of VLSI Systems. - David de Andrés; Juan-Carlos Ruiz-Garcia 001; Daniel Gil; Pedro J. Gil (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Technologies for the Development of Dependable and Secure Component-based Embedded Systems: TecnoSeC Project. - Juan Pardo; David de Andrés; Juan Carlos Ruiz 001; José Carlos Campelo (ESA, 2009)

Design and Deployment of a Generic ECC-based Fault Tolerance Mechanism for Embedded HW Cores. - Juan-Carlos Ruiz-Garcia 001; David de Andrés; Pedro J. Gil (ETFA, 2009)

Using Dependability, Performance, Area and Energy Consumption Experimental Measures to Benchmark IP Cores. - David de Andrés; Juan-Carlos Ruiz-Garcia 001; Pedro J. Gil (LADC, 2009)

An Attack Injection Approach to Evaluate the Robustness of Ad Hoc Networks. - David de Andrés; Jesus Friginal; Juan-Carlos Ruiz-Garcia 001; Pedro J. Gil (PRDC, 2009)

Attack Injection to Support the Evaluation of Ad Hoc Networks. - Jesus Friginal; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Pedro J. Gil (SRDS, 2010)

Coarse-grained resilience benchmarking using logic score of preferences: ad hoc networks as a case study. - Jesus Friginal; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Pedro J. Gil (EWDC, 2011)

On Selecting Representative Faultloads to Guide the Evaluation of Ad Hoc Networks. - Jesus Friginal; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Pedro J. Gil (LADC, 2011)

Using Performance, Energy Consumption, and Resilience Experimental Measures to Evaluate Routing Protocols for Ad Hoc Networks. - Jesus Friginal; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Pedro J. Gil (NCA, 2011)

Using Dependability Benchmarks to Support ISO/IEC SQuaRE. - Jesus Friginal; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Regina Moraes (PRDC, 2011)

Resilience-Driven Parameterisation of Ad Hoc Routing Protocols: olsrd as a Case Study. - Jesus Friginal; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Pedro J. Gil (SRDS, 2011)

Towards benchmarking routing protocols in wireless mesh networks. - Jesus Friginal; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Pedro J. Gil (Ad Hoc Networks, 2011)

An aspect-oriented approach to face neighbour saturation issues in proactive ad hoc routing protocols: olsrd as a case study. - Antonio Bustos; Jesús Friginal; David de Andrés; Juan Carlos Ruiz 001 (ARMOR, 2012)

Towards changing the user perception of mobile communications through geotagged information. - Miquel Martínez; David de Andrés; Juan Carlos Ruiz 001; Mahbub Hassan; Salil S. Kanhere (ARMOR, 2012)

Mitigating the impact of ambient noise on Wireless Mesh Networks using adaptive link-quality-based packet replication. - Jesus Friginal; Juan-Carlos Ruiz-Garcia 001; David de Andrés; Antonio Bustos (DSN, 2012)

Tolerating multiple faults with proximate manifestations in FPGA-based critical designs for harsh environments. - Jaime Espinosa; David de Andrés; Juan Carlos Ruiz 001; Pedro J. Gil (FPL, 2012)

Fault Tolerance on NoCs. - José Miguel Montañana; David de Andrés; Francisco Tirado (AINA Workshops, 2013)

The Challenge of Detection and Diagnosis of Fugacious Hardware Faults in VLSI Designs. - Jaime Espinosa; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Pedro J. Gil (EWDC, 2013)

Improving the Transfer of Safety and Security Competences to Industry: The RISKY Approach. - Joaquin Gracia-Moran; Juan-Carlos Ruiz-Garcia 001; Juan-Carlos Baraza-Calvo; David de Andrés; Pedro J. Gil (EWDC, 2013)

Open Challenges in the Resilience Evaluation of Ad Hoc Networks. - Miquel Martínez; Jesus Friginal; David de Andrés; Juan-Carlos Ruiz-Garcia 001 (EWDC, 2013)

Analysis of results in dependability benchmarking: Can we do better? - Miquel Martínez; David de Andrés; Juan Carlos Ruiz 001; Jesus Friginal (M&N, 2013)

Preventing Memory Errors in Networked Vehicle Services Through Diversification. - Hector Marco-Gisbert; Juan Carlos Ruiz 001; David de Andrés; Ismael Ripoll (CARS@SAFECOMP, 2013)

Gaining Confidence on Dependability Benchmarks' Conclusions through "Back-to-Back" Testing (Practical Experience Report). - Miquel Martínez; David de Andrés; Juan-Carlos Ruiz-Garcia 001 (EDCC, 2014)

A survey of evaluation platforms for ad hoc routing protocols: A resilience perspective. - Jesus Friginal; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Miquel Martínez (Comput. Networks, 2014)

Ambient noise in wireless mesh networks: Evaluation and proposal of an adaptive algorithm to mitigate link removal. - Jesus Friginal; Juan-Carlos Ruiz-Garcia 001; David de Andrés; Antonio Bustos (J. Netw. Comput. Appl., 2014)

From Measures to Conclusions Using Analytic Hierarchy Process in Dependability Benchmarking. - Miquel Martínez; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Jesus Friginal (IEEE Trans. Instrum. Meas., 2014)

Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification. - Jaime Espinosa; Carles Hernández 001; Jaume Abella 001; David de Andrés; Juan-Carlos Ruiz-Garcia 001 (DAC, 2015)

Increasing the Dependability of VLSI Systems through Early Detection of Fugacious Faults. - Jaime Espinosa; David de Andrés; Pedro J. Gil (EDCC, 2015)

REFRAHN: A Resilience Evaluation Framework for Ad Hoc Routing Protocols. - Jesus Friginal; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Miquel Martínez (Comput. Networks, 2015)

Speeding-Up Simulation-Based Fault Injection of Complex HDL Models. - Ilya Tuzov; Juan Carlos Ruiz 001; David de Andrés; Pedro J. Gil (LADC, 2016)

Multi-criteria analysis of measures in benchmarking: Dependability benchmarking as a case study. - Jesus Friginal; Miquel Martínez; David de Andrés; Juan-Carlos Ruiz-Garcia 001 (J. Syst. Softw., 2016)

Dependability-Aware Design Space Exploration for Optimal Synthesis Parameters Tuning. - Ilya Tuzov; David de Andrés; Juan Carlos Ruiz 001 (DSN, 2017)

Accurately Simulating the Effects of Faults in VHDL Models Described at the Implementation-Level. - Ilya Tuzov; Juan Carlos Ruiz 001; David de Andrés (EDCC, 2017)

DAVOS: EDA Toolkit for Dependability Assessment, Verification, Optimisation and Selection of Hardware Models. - Ilya Tuzov; David de Andrés; Juan Carlos Ruiz 001 (DSN, 2018)

Accurate Robustness Assessment of HDL Models Through Iterative Statistical Fault Injection. - Ilya Tuzov; David de Andrés; Juan Carlos Ruiz 001 (EDCC, 2018)

Speeding-Up Robustness Assessment of HDL Models through Profiling and Multi-Level Fault Injection. - Ilya Tuzov; David de Andrés; Juan Carlos Ruiz 001 (LADC, 2018)

Tuning synthesis flags to optimize implementation goals: Performance and robustness of the LEON3 processor as a case study. - Ilya Tuzov; David de Andrés; Juan Carlos Ruiz 001 (J. Parallel Distributed Comput., 2018)

Robustness-Aware Design Space Exploration Through Iterative Refinement of D-Optimal Designs. - Ilya Tuzov; David de Andrés; Juan Carlos Ruiz 001 (EDCC, 2019)

Simulating the effects of logic faults in implementation-level VITAL-compliant models. - Ilya Tuzov; David de Andrés; Juan Carlos Ruiz 001 (Computing, 2019)

Improving Robustness-Aware Design Space Exploration for FPGA-Based Systems. - Ilya Tuzov; David de Andrés; Juan Carlos Ruiz 001 (EDCC, 2020)

Reversing FPGA architectures for speeding up fault injection: does it pay? - Ilya Tuzov; David de Andrés; Juan Carlos Ruiz 001 (EDCC, 2022)

A Multi-Criteria Analysis of Benchmark Results With Expert Support for Security Tools. - Miquel Martínez; Juan Carlos Ruiz 001; Nuno Antunes; David de Andrés; Marco Vieira (IEEE Trans. Dependable Secur. Comput., 2022)

BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes. - Ilya Tuzov; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Carles Hernández 001 (DATE, 2023)

Zero-Space In-Weight and In-Bias Protection for Floating-Point-based CNNs. - Juan Carlos Ruiz 001; David de Andrés; Luis J. Saiz-Adalid; Joaquin Gracia-Moran (EDCC, 2024)

Allocating ECC parity bits into BF16-encoded CNN parameters: A practical experience report. - Joaquin Gracia-Moran; Juan Carlos Ruiz 001; David de Andrés; Luis J. Saiz-Adalid (LADC, 2024)

In-Memory Zero-Space Floating-Point-Based CNN Protection Using Non-significant and Invariant Bits. - Juan Carlos Ruiz 001; David de Andrés; Luis J. Saiz-Adalid; Joaquin Gracia-Moran (SAFECOMP, 2024)

Can C-Based ECC Models Leverage High-Level Synthesis? Evaluating Description Variants for Efficient Circuit Implementations. - Joaquin Gracia-Moran; Juan-Carlos Ruiz-Garcia 001; David de Andrés; Luis J. Saiz-Adalid (SAFECOMP, 2025)