Design methodology for IBM ASIC products. - James J. Engel; Thomas S. Guzowski; Anderson Hunt; David E. Lackey; Lansing D. Pickup; Robert A. Proctor; Karla Reynolds; Ann Marie Rincon; David R. Stauffer (IBM J. Res. Dev., 1996)

Applying placement-based synthesis for on-time system-on-a-chip design. - David E. Lackey (CICC, 2000)

Managing power and performance for System-on-Chip designs using Voltage Islands. - David E. Lackey; Paul S. Zuchowski; Thomas R. Bednar; Douglas W. Stout; Scott W. Gould; John M. Cohn (ICCAD, 2002)

The IBM ASIC/SoC methodology - A recipe for first-time success. - George W. Doerre; David E. Lackey (IBM J. Res. Dev., 2002)

IBM's 50 Million gate ASICs. - Jürgen Koehl; David E. Lackey; George W. Doerre (ASP-DAC, 2003)

Designing mega-ASICs in nanogate technologies. - David E. Lackey; Paul S. Zuchowski; Jürgen Koehl (DAC, 2003)

Efficient Latch and Clock Structures for System-on-Chip Test Flexibility. - David E. Lackey (ITC, 2006)

Variation-aware performance verification using at-speed structural test and statistical timing. - Vikram Iyengar; Jinjun Xiong; Subbayyan Venkatesan; Vladimir Zolotov; David E. Lackey; Peter A. Habitz; Chandu Visweswariah (ICCAD, 2007)

An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs. - Vikram Iyengar; Kenneth Pichamuthu; Andrew Ferko; Frank Woytowich; David E. Lackey; Gary Grise; Mark Taylor 001; Mike Degregorio; Steven F. Oakland (VTS, 2007)

Low cost at-speed testing using On-Product Clock Generation compatible with test compression. - Brion L. Keller; Krishna Chakravadhanula; Brian Foutz; Vivek Chickermane; R. Malneedi; Thomas J. Snethen; Vikram Iyengar; David E. Lackey; Gary Grise (ITC, 2010)