Plug-in timing models for an abstract timing verifier. - David E. Wallace; Carlo H. Séquin (DAC, 1986)

ATV: An Abstract Timing Verifier. - David E. Wallace; Carlo H. Séquin (DAC, 1988)

High-Level Delay Estimation for Technology-Independent Logic Equations. - David E. Wallace; Mandalagiri S. Chandrasekhar (ICCAD, 1990)

Effective Coupling Between Logic Synthesis and Layout Tools for Synthesis of Area and Speed-Efficient Circuits. - Mandalagiri S. Chandrasekhar; Robert H. McCharles; David E. Wallace (VLSI Design, 1997)