Closing the gap between ASIC and custom: an ASIC perspective. - David G. Chinnery; Kurt Keutzer (DAC, 2000)

Achieving 550Mhz in an ASIC Methodology. - David G. Chinnery; Borivoje Nikolic; Kurt Keutzer (DAC, 2001)

A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage. - Serdar Tasiran; Farzan Fallah; David G. Chinnery; Scott J. Weber; Kurt Keutzer (ICCD, 2001)

Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition. - Masayuki Ito; David G. Chinnery; Kurt Keutzer (ICCD, 2003)

Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. - David Nguyen; Abhijit Davare; Michael Orshansky; David G. Chinnery; Brandon Thompson; Kurt Keutzer (ISLPED, 2003)

Closing the Gap Between ASIC and Custom - Tools and Techniques for High-Performance ASIC Design. - David G. Chinnery; Kurt Keutzer (Springer, 2004)

Closing the power gap between ASIC and custom: an ASIC perspective. - David G. Chinnery; Kurt Keutzer (DAC, 2005)

Linear programming for sizing, Vth and Vdd assignment. - David G. Chinnery; Kurt Keutzer (ISLPED, 2005)

Closing the Power Gap between ASIC and Custom - Tools and Techniques for Low Power Design. - David G. Chinnery; Kurt Keutzer (Springer, 2007)

High performance and low power design techniques for ASIC and custom in nanometer technologies. - David G. Chinnery (ISPD, 2013)

ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement. - Vladimir Yutsis; Ismail Bustany; David G. Chinnery; Joseph R. Shinnerl; Wen-Hao Liu 001 (ISPD, 2014)

Fast Lagrangian Relaxation Based Gate Sizing using Multi-Threading. - Ankur Sharma 001; David G. Chinnery; Sarvesh Bhardwaj; Chris C. N. Chu (ICCAD, 2015)

ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement. - Ismail S. Bustany; David G. Chinnery; Joseph R. Shinnerl; Vladimir Yutsis (ISPD, 2015)

Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation. - Ioannis Seitanidis; Giorgos Dimitrakopoulos; Pavlos M. Mattheakis; Laurent Masse-Navette; David G. Chinnery (DAC, 2017)

Rapid gate sizing with fewer iterations of Lagrangian Relaxation. - Ankur Sharma 001; David G. Chinnery; Shrirang Dhamdhere; Chris Chu (ICCAD, 2017)

Session details: Detailed Routing Contest Results. - David G. Chinnery (ISPD, 2019)

Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling - A Fast and Effective Approach. - Ankur Sharma 001; David G. Chinnery; Chris Chu (ISPD, 2019)

Timing-Driven and Placement-Aware Multibit Register Composition. - Ioannis Seitanidis; Giorgos Dimitrakopoulos; Pavlos M. Mattheakis; Laurent Masse-Navette; David G. Chinnery (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian Relaxation. - Apostolos Stefanidis; Dimitrios Mangiras; Chrysostomos Nicopoulos; David G. Chinnery; Giorgos Dimitrakopoulos (ISPD, 2020)

Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations. - Ankur Sharma 001; David G. Chinnery; Tiago Reimann; Sarvesh Bhardwaj; Chris Chu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based Optimization. - Apostolos Stefanidis; Dimitrios Mangiras; Chrysostomos Nicopoulos; David G. Chinnery; Giorgos Dimitrakopoulos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Integrating LR Gate Sizing in an Industrial Place-and-Route Flow. - David G. Chinnery; Ankur Sharma 001 (ISPD, 2022)

EDA for Domain Specific Computing: An Introduction for the Panel. - Iris Hui-Ru Jiang; David G. Chinnery (ISPD, 2023)

Task-Based Parallel Programming for Gate Sizing. - Dimitrios Mangiras; David G. Chinnery; Giorgos Dimitrakopoulos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Introduction to the Special Section on Advances in Physical Design Automation. - Iris Hui-Ru Jiang; David G. Chinnery; Gracieli Posser; Jens Lienig (ACM Trans. Design Autom. Electr. Syst., 2023)