A 64-b microprocessor with multimedia support. - Lavi Lev; Andy Charnas; Marc Tremblay; Alexander Dalal; Bruce A. Frederick; Chakra R. Srivatsa; David Greenhill; Dennis L. Wendell; Duy Dinh Pham; Eric Anderson; Hemraj K. Hingarh; Inayat Razzack; et al. (IEEE J. Solid State Circuits, 1995)

An 8-Core 64-Thread 64b Power-Efficient SPARC SoC. - Umesh Gajanan Nawathe; Mahmudul Hassan; Lynn Warriner; King C. Yen; Bharat Upputuri; David Greenhill; Ashok Kumar; Heechoul Park (ISSCC, 2007)

Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip. - Umesh Gajanan Nawathe; Mahmudul Hassan; King C. Yen; Ashok Kumar; Aparna Ramachandran; David Greenhill (IEEE J. Solid State Circuits, 2008)

A 40nm 16-core 128-thread CMT SPARC SoC processor. - Jinuk Luke Shin; Kenway W. Tam; Dawei Huang; Bruce Petrick; Ha Pham; Changku Hwang; Hongping Penny Li; Alan P. Smith 002; Timothy Johnson; Francis Schumacher; David Greenhill; Ana Sonia Leon; et al. (ISSCC, 2010)

3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration. - David Greenhill; Ron Ho; David M. Lewis; Herman Schmit; Kok Hong Chan; Andy Tong; Sean Atsatt; Dana How; Peter McElheny; Keith Duwel; Jeffrey Schulz; Darren Faulkner; et al. (ISSCC, 2017)