A microprogrammable processor using single poly EPROM. - Kenneth J. Schultz; David H. K. Hoe; C. André T. Salama (Integr., 1989)

Cell and circuit design for single-poly EPROM. - David H. K. Hoe; Kenneth J. Schultz; C. André T. Salama; Robert A. Hadaway; Paul Kempf (IEEE J. Solid State Circuits, 1989)

GaAs pipelined dynamic logic. - David H. K. Hoe; C. André T. Salama (Integr., 1991)

GaAs trickle transistor dynamic logic. - David H. K. Hoe; C. André T. Salama (IEEE J. Solid State Circuits, 1991)

An auto-ranging photodiode preamplifier with 114 dB dynamic range. - David H. K. Hoe; David B. Ribner (IEEE J. Solid State Circuits, 1996)

An efficient FPGA random number generator using LFSRs and cellular automata. - Juan C. Cerda; Chris D. Martinez; Jonathan M. Comer; David H. K. Hoe (MWSCAS, 2012)

Optimization of short channel CMOS LNAs by geometric programming. - Xiaoyu Jin; David H. K. Hoe (MWSCAS, 2012)

Cellular Automata-Based Parallel Random Number Generators Using FPGAs. - David H. K. Hoe; Jonathan M. Comer; Juan C. Cerda; Chris D. Martinez; Mukul V. Shirvaikar (Int. J. Reconfigurable Comput., 2012)

Development of a concept inventory for microelectronics courses. - David H. K. Hoe (FIE, 2013)

Designing an agent based model for the efficient removal of red imported fire ant colonies. - James Ford Johnson; David H. K. Hoe (SummerSim, 2013)

Image segmentation on GPGPUs: a cellular automata-based approach. - Irving Olmedo; Yessika Guerra Perez; James Ford Johnson; Lakshman Raut; David H. K. Hoe (SummerSim, 2013)

FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders. - David H. K. Hoe; L. P. Deepthi Bollepalli; Chris D. Martinez (VLSI Design, 2013)

Designing Stealthy Trojans with Sequential Logic: A Stream Cipher Case Study. - Mukesh Reddy Rudra; Nimmy Anna Daniel; Varun Nagoorkar; David H. K. Hoe (DAC, 2014)

Towards Secure Analog Designs: A Secure Sense Amplifier Using Memristors. - David H. K. Hoe; Jeyavijayan Rajendran; Ramesh Karri (ISVLSI, 2014)

The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach. - David H. K. Hoe; Xiaoyu Jin (VLSI Design, 2015)

Bayesian inference using spintronic technology: A proposal for an MRAM-based stochastic logic gate. - David H. K. Hoe (MWSCAS, 2017)

Implementing Stochastic Bayesian Inference : Design of the Stochastic Number Generators. - David H. K. Hoe; Chet Pajardo II (MWSCAS, 2019)

Bayesian inference using stochastic logic: A study of buffering schemes for mitigating autocorrelation. - David H. K. Hoe (Int. J. Approx. Reason., 2019)

The Impact of Noise on Quantum Adder Circuits: An IBM Quantum Case Study. - Jefferson Rice; David H. K. Hoe (MWSCAS, 2024)