Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors. - Alex Park 002; Venkat Narayanan; Keith A. Bowman; Francois Atallah; Alain Artieri; Sei Seung Yoon; Kendrick Yuen; David Hansquine (CICC, 2014)

Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processors. - Keith A. Bowman; Alex Park 002; Venkat Narayanan; Francois Atallah; Alain Artieri; Sei Seung Yoon; Kendrick Yuen; David Hansquine (ITC, 2014)

A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells. - Jihoon Jeong; Francois Atallah; Hoan Nguyen; Josh Puckett; Keith A. Bowman; David Hansquine (CICC, 2015)

8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range. - Keith A. Bowman; Sarthak Raina; Todd Bridges; Daniel Yingling; Hoan Nguyen; Brad Appel; Yesh Kolla; Jihoon Jeong; Francois Atallah; David Hansquine (ISSCC, 2015)

A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range. - Keith A. Bowman; Sarthak Raina; Todd Bridges; Daniel Yingling; Hoan Nguyen; Brad Appel; Yesh Kolla; Jihoon Jeong; Francois Atallah; David Hansquine (IEEE J. Solid State Circuits, 2016)