Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. - Yasunobu Nakase; Yoshikazu Morooka; David J. Perlman; Daniel J. Kolor; Jae-Myoung Choi; Hyun J. Shin; Tsutomu Yoshimura; Naoya Watanabe; Yoshio Matsuda; Masaki Kumanoya; Michihiro Yamada (IEEE J. Solid State Circuits, 1999)