Ultra-low power flip-flops for MTCMOS circuits. - David Levacq; Vincent Dessard; Denis Flandre (ISCAS (5), 2005)

A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOS. - David Levacq; Takuya Minakawa; Makoto Takamiya; Takayasu Sakurai (CICC, 2007)

Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution. - David Levacq; Muhammad Yazid; Hiroshi Kawaguchi 001; Makoto Takamiya; Takayasu Sakurai (ESSCIRC, 2007)

Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode. - David Levacq; Vincent Dessard; Denis Flandre (IEEE J. Solid State Circuits, 2007)

Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder. - David Bol; Ilham Hassoune; David Levacq; Denis Flandre; Jean-Didier Legat (J. Multiple Valued Log. Soft Comput., 2007)

1/5 power reduction by global optimization based on fine-grained body biasing. - Yasumi Nakamura; David Levacq; Limin Xiao; Takuya Minakawa; Taro Niiyama; Makoto Takamiya; Takayasu Sakurai (CICC, 2008)

Backgate Bias Accelerator for sub-100 ns Sleep-to-Active Modes Transition Time. - David Levacq; Makoto Takamiya; Takayasu Sakurai (IEEE J. Solid State Circuits, 2008)

112-Gbps High Speed Serial Links to Interconnect Direct RF Sampling ADCs and Digital High Throughput Satellite Processors. - Adem Coskun; Salvatore D'Addio; Richard Jansen; David Levacq; Piero Angeletti (MeditCom, 2024)