A hardware engine for analogue mode simulation of MOS digital circuits. - David M. Lewis (DAC, 1985)

Swamp: A Fast Processor for Smalltalk-80. - David M. Lewis; David R. Galloway; Robert J. Francis; Brian W. Thomson (OOPSLA, 1986)

A Programmable Hardware Accelerator for Compiled Electrical Simulation. - David M. Lewis (DAC, 1988)

Hardware accelerators for timing simulation of VLSI digital circuits. - David M. Lewis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Transforming bit-serial communication circuits into fast parallel VLSI implementations. - David M. Lewis; Brian W. Thomson; Peter I. P. Boulton; E. Stewart Lee (IEEE J. Solid State Circuits, 1988)

Algorithm design for a 30-bit integrated logarithmic processor. - David M. Lewis; Lawrence K. Yu (IEEE Symposium on Computer Arithmetic, 1989)

Hierarchical compiled event-driven logic simulation. - David M. Lewis (ICCAD, 1989)

Using Deducibility in Secure Network Modelling. - Brian W. Thomson; E. Stewart Lee; Peter I. P. Boulton; Michael Stumm; David M. Lewis (ESORICS, 1990)

An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System. - David M. Lewis (IEEE Trans. Computers, 1990)

Device model approximation using 2N trees. - David M. Lewis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency. - Jonathan Rose; Robert J. Francis; David M. Lewis; Paul Chow (IEEE J. Solid State Circuits, 1990)

Hector: A Hierarchically Structured Shared-memory Multiprocessor. - Zvonko G. Vranesic; Michael Stumm; David M. Lewis; Ron White (Computer, 1991)

A hierarchical compiled code event-driven logic simulator. - David M. Lewis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

A 30-b integrated logarithmic number system processor. - Lawrence K. Yu; David M. Lewis (IEEE J. Solid State Circuits, 1991)

A compiled-code hardware accelerator for circuit simulation. - David M. Lewis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

The effect of logic block architecture on FPGA performance. - Satwant Singh; Jonathan Rose; Paul Chow; David M. Lewis (IEEE J. Solid State Circuits, 1992)

An accurate LNS arithmetic unit using interleaved memory function interpolator. - David M. Lewis (IEEE Symposium on Computer Arithmetic, 1993)

A Field Programmable Accelerator for Compiled-Code Applications. - David M. Lewis; Marcus van Ierssel; Daniel H. Wong (ICCD, 1993)

Highly Selective "Analog" Filters Using Delta Sigma Based IIR Filtering. - David A. Johns; David M. Lewis; Don Cherepacha (ISCAS, 1993)

A multiple-strength multiple-delay compiled-code logic simulator. - Ahmet N. Parlakbilek; David M. Lewis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Routing Architectures for Hierarchical Field Programmable Gate Arrays. - Aditya A. Aggarwal; David M. Lewis (ICCD, 1994)

Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit. - David M. Lewis (IEEE Trans. Computers, 1994)

114 MFLOPS logarithmic number system arithmetic unit for DSP applications. - David M. Lewis (IEEE J. Solid State Circuits, 1995)

Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays. - Vi Cuong Chan; David M. Lewis (FPGA, 1996)

Atmospheric diffusion: some new mathematical models. - P. C. Chatwin; David M. Lewis; Nils Mole (Adv. Comput. Math., 1996)

DP-FPGA: An FPGA Architecture Optimized for Datapaths. - Don Cherepacha; David M. Lewis (VLSI Design, 1996)

Automated field-programmable compute accelerator design using partial evaluation. - Qiang Wang; David M. Lewis (FCCM, 1997)

The Transmogrifier-2: a 1 million gate rapid-prototyping system. - David M. Lewis; David R. Galloway; Marcus van Ierssel; Jonathan Rose; Paul Chow (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Procedural Texture Mapping on FPGAs. - Andy Gean Ye; David M. Lewis (FPGA, 1999)

Design of a VLIW Compute Accelerator on the Transmogrifier-2. - L. Louis Zhang; Qiang Wang; David M. Lewis (FCCM, 2000)

Generating highly-routable sparse crossbars for PLDs. - Guy G. Lemieux; Paul Leventis; David M. Lewis (FPGA, 2000)

Using sparse crossbars within LUT. - Guy G. Lemieux; David M. Lewis (FPGA, 2001)

Circuit design of routing switches. - Guy G. Lemieux; David M. Lewis (FPGA, 2002)

Analytical Framework for Switch Block Design. - Guy G. Lemieux; David M. Lewis (FPL, 2002)

Synthesizing datapath circuits for FPGAs with emphasis on area minimization. - Andy Gean Ye; Jonathan Rose; David M. Lewis (FPT, 2002)

Cyclone ™: a low-cost, high-performance FPGA. - Paul Leventis; Mark Chan; Michael Chan; David M. Lewis; Behzad Nouban; Giles Powell; Brad Vest; Myron Wong; Renxin Xia; John Costello (CICC, 2003)

Architecture of datapath-oriented coarse-grain logic and routing for FPGAs. - Andy Gean Ye; Jonathan Rose; David M. Lewis (CICC, 2003)

The StratixTM routing and logic architecture. - David M. Lewis; Vaughn Betz; David Jefferson; Andy Lee; Christopher Lane; Paul Leventis; Sandy Marquardt; Cameron McClintock; Bruce Pedersen; Giles Powell; Srinivas Reddy; Chris Wysocki; et al. (FPGA, 2003)

MAX II: A low-cost, high-performance LUT-based CPLD. - Paul Leventis; Brad Vest; Mike Hutton; David M. Lewis (CICC, 2004)

Improving FPGA Performance and Area Using an Adaptive Logic Module. - Michael D. Hutton; Jay Schleicher; David M. Lewis; Bruce Pedersen; Richard Yuan; Sinan Kaptanoglu; Gregg Baeckler; Boris Ratchev; Ketan Padalia; Mark Bourgeault; Andy Lee; Henry Kim; et al. (FPL, 2004)

The Stratix II logic and routing architecture. - David M. Lewis; Elias Ahmed; Gregg Baeckler; Vaughn Betz; Mark Bourgeault; David Cashman; David R. Galloway; Mike Hutton; Christopher Lane; Andy Lee; Paul Leventis; Sandy Marquardt; et al. (FPGA, 2005)

Architectural enhancements in Stratix-IIITM and Stratix-IVTM. - David M. Lewis; Elias Ahmed; David Cashman; Tim Vanderhoek; Christopher Lane; Andy Lee; Philip Pan (FPGA, 2009)

A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs. - Doris Chen; Deshanand P. Singh; Jeffrey Chromczak; David M. Lewis; Ryan Fung; David Neto; Vaughn Betz (FPGA, 2010)

An Empirical Evaluation of Similarity Coefficients for Binary Valued Data. - David M. Lewis; Vandana Pursnani Janeja (Int. J. Data Warehous. Min., 2011)

Architectural enhancements in Stratix V™. - David M. Lewis; David Cashman; Mark Chan; Jeffrey Chromczak; Gary Lai; Andy Lee; Tim Vanderhoek; Haiming Yu (FPGA, 2013)

Arria™ 10 device architecture. - Jeffrey Tyhach; Mike Hutton; Sean Atsatt; Arifur Rahman; Brad Vest; David M. Lewis; Martin Langhammer; Sergey Y. Shumarayev; Tim Hoang; Allen Chan; Dong-Myung Choi; Dan Oh; et al. (CICC, 2015)

Stratix™ 10 High Performance Routable Clock Networks. - Carl Ebeling; Dana How; David M. Lewis; Herman Schmit (FPGA, 2016)

The Stratix™ 10 Highly Pipelined FPGA Architecture. - David M. Lewis; Gordon R. Chiu; Jeffrey Chromczak; David R. Galloway; Ben Gamsa; Valavan Manohararajah; Ian Milton; Tim Vanderhoek; John Van Dyken (FPGA, 2016)

3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration. - David Greenhill; Ron Ho; David M. Lewis; Herman Schmit; Kok Hong Chan; Andy Tong; Sean Atsatt; Dana How; Peter McElheny; Keith Duwel; Jeffrey Schulz; Darren Faulkner; et al. (ISSCC, 2017)

Spatial Timing Analysis With Exact Propagation of Delay and Application to FPGA Performance. - David M. Lewis; Herman Schmit (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)